[FIRRTL] InferWidths failures

[dtzSiFive]

h/t @uenoku

Looks like #5403 causes problems on designs that should work.

Sample inputs:

circuit Widths:
  module Widths:
    input y : UInt<2>
    output out1 : UInt

    wire w : UInt
    w <= UInt(0)
    w <= y

    out1 <= w

->

widths-2.fir:6:5: error: uninferred width: wire "w" cannot satisfy all width requirements
    wire w : UInt
    ^
widths-2.fir:8:7: note: width is constrained to be at least 2 here:
    w <= y
      ^
widths-2.fir:8:7: note: width is constrained to be at most 1 here:

---

circuit Widths:
  module Widths:
    input x : UInt<1>
    input y : UInt<2>
    output out1 : UInt

    wire w : UInt
    w <= x
    w <= y

    out1 <= w

->

widths-3.fir:7:5: error: uninferred width: wire "w" cannot satisfy all width requirements
    wire w : UInt
    ^
widths-3.fir:9:7: note: width is constrained to be at least 2 here:
    w <= y
      ^
widths-3.fir:9:7: note: width is constrained to be at most 1 here: