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[SV] SVExtractTestCode not Extracting Assert Properties #6864

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seldridge opened this issue Mar 22, 2024 · 0 comments · Fixed by #6865
Closed

[SV] SVExtractTestCode not Extracting Assert Properties #6864

seldridge opened this issue Mar 22, 2024 · 0 comments · Fixed by #6865

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@seldridge
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seldridge commented Mar 22, 2024

The following code example results in an unextracted assertion:

hw.module @Foo(in %a : i1, in %b : i1) {
  %true = hw.constant true
  %0 = comb.xor bin %b, %true : i1
  %1 = ltl.delay %true, 1, 0 : i1
  %2 = ltl.concat %a, %1 : i1, !ltl.sequence
  %3 = ltl.implication %2, %0 : !ltl.sequence, i1
  verif.assert %3 label "foo" : !ltl.property
  hw.output
}

This produces with circt-opt -sv-extract-test-code:

hw.module @Foo(in %a : i1, in %b : i1) {
  %true = hw.constant true
  %0 = comb.xor bin %b, %true : i1
  %1 = ltl.delay %true, 1, 0 : i1
  %2 = ltl.concat %a, %1 : i1, !ltl.sequence
  %3 = ltl.implication %2, %0 : !ltl.sequence, i1
  verif.assert %3 label "foo" : !ltl.property
  hw.output
}
seldridge added a commit that referenced this issue Mar 22, 2024
Fix a bug where SVExtractTestCode was not extracting asserts, assumes, and
covers from the verif dialect.  This resulted in unexpected end-to-end
"failures" from Chisel where Chisel asserts, assumes, and covers were not
extracted and left in the design.

Fixes #6864.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
seldridge added a commit that referenced this issue Mar 24, 2024
Fix a bug where SVExtractTestCode was not extracting asserts, assumes, and
covers from the verif dialect.  This resulted in unexpected end-to-end
"failures" from Chisel where Chisel asserts, assumes, and covers were not
extracted and left in the design.

Fixes #6864.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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