Commits on Apr 25, 2023

1. [ExportVerilog] Add support for UnionCreate op. …

   This adds support for `hw::UnionCreateOp` to ExportVerilog.  It works by
   emitting a bit concatenation and assigning it to a wire with a union
   type.  Each union member may have a prepadding, which is decided by the
   member's offset size, and a postpadding to ensure that each union
   element is the same size. The resulting bitconcat is `{prepadding, data,
   postpadding}`.  If there is no padding for a particular member, then
   bitconcat will not be used.
   
   The following example has no offsets, but the member `a` requires
   post-padding of `1` bit.
   
   ```mlir
   hw.module @unionCreate(%in: i1) -> (out: !hw.union<a: i1, b: i2>) {
       %0 = hw.union_create "a", %in : !hw.union<a: i1, b: i2>
       hw.output %0 : !hw.union<a: i1, b: i2>
   }
   ```
   
   ```verilog
   module unionCreate(
     input                                                                                          in,
     output union packed { struct packed {logic a; logic [0:0] __post_padding_a;} a;logic [1:0] b;} out
   );
   
     assign out = {in, 1'h0};
   endmodule
   ```

   

   youngar committed Apr 25, 2023
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