Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

[OM] Bypass constant ops referencing symbols in ExportVerilog #5314

Merged
merged 1 commit into from
Jun 5, 2023
Merged

[OM] Bypass constant ops referencing symbols in ExportVerilog #5314

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 3 additions & 0 deletions lib/Conversion/ExportVerilog/ExportVerilog.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5730,6 +5730,9 @@ void SharedEmitterState::gatherFiles(bool separateModules) {
.Case<om::ClassOp>([&](auto op) {
symbolCache.addDefinition(op.getSymNameAttr(), op);
})
.Case<om::ConstantOp>([&](auto op) {
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Just wondering, do we create arbitrary OM operations under the top-level operations? I'm not sure it's expected but if so, I think we might want to just accept all OM operations not only limited to constant.

// Constant ops might reference symbols, skip them.
})
.Default([&](auto *) {
op.emitError("unknown operation (SharedEmitterState::gatherFiles)");
encounteredError = true;
Expand Down