[LowerToHW] Implement MuxCell intrinsics lowering

[uenoku]

This commit deprecates addMuxPragma flag in LowerToHW and implements lowering of MuxCell intrinsics.

MuxCell intrinsics are lowered into a wire declaration, an assignment with infer_mux_override pragma and a value with map_to_mux pragma. Operands are probed to hw.wire with inner symbols to prevent optimizations from destructing AST structures.

[uenoku]

This looks a bit complicated but this is an example that produces incorrect results if CSE prevention was not added.

[uenoku]

circuit Mux2Cell: 
  intmodule Mux2:
     input sel: UInt<1>
     input high: UInt
     input low: UInt
     output out: UInt
     intrinsic = circt_mux2cell

  extmodule Val:
     output v: UInt<1>
  module Mux2Cell:
    input cond: UInt<1>
    input low: UInt<1>
    output out: UInt<1>[2]
    wire w: UInt<1>
    inst mux2 of Mux2
    inst ext of Val
    w <= ext.v
    mux2.sel <= xor(cond, UInt<1>(1))
    mux2.high <= w
    mux2.low <= low
    out[0] <= mux2.out
    inst mux2_1 of Mux2
    mux2_1.sel <= xor(cond, UInt<1>(1))
    mux2_1.high <= ext.v
    mux2_1.low <= low
    out[1] <= mux2_1.out

This is the output verilog when we didn't do CSE prevention. _GEN ? /* cadence map_to_mux */ _ext_v : low; is spilled to a wire because of the multiple uses. As a result /* synopsys infer_mux_override */ is located in an invalid place.

// Generated by CIRCT firtool-1.44.0-88-gdf6361bc3
// external module Val

module Mux2Cell(
  input  cond,
         low,
  output out_0,
         out_1
);

  wire _GEN;
  wire _ext_v;
  wire _GEN_0 = _GEN ? /* cadence map_to_mux */ _ext_v : low;
  wire _GEN_1;
  /* synopsys infer_mux_override */
  assign _GEN_1 = _GEN_0;
  assign _GEN = ~cond;
  wire _GEN_2;
  /* synopsys infer_mux_override */
  assign _GEN_2 = _GEN_0;
  Val ext (
    .v (_ext_v)
  );
  assign out_0 = _GEN_1;
  assign out_1 = _GEN_2;
endmodule

[uenoku]

I changed to use hw.wires and inner symbols to block optimizations so that we can keep AST structures. I'm going to merge the PR but post commit review is welcomed.

[darthscsi]

OrderedOutputOp might help keep things in the right order. (or similar)