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[Pipeline] Add per-register clock gating #5489

Merged
merged 3 commits into from
Jul 3, 2023
Merged

[Pipeline] Add per-register clock gating #5489

merged 3 commits into from
Jul 3, 2023

Commits on Jun 30, 2023

  1. [Pipeline] Add per-register clock gating 

    Also changes to that the `clock-gate-regs` options actually implements clock gates instead of a `seq.comp_reg.ce` operation. To cover all cases, i think there needs to be three kinds of gating implementations - clock gate, clock enable (`seq.compreg.ce`) and input muxing. The first and last are what we have now.
    @mortbopet
    mortbopet committed Jun 30, 2023
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  2. tidy

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    mortbopet committed Jun 30, 2023
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  3. review comments + fix register names

    @mortbopet
    mortbopet committed Jun 30, 2023
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