[LegalizeDAG] Fix MSVC "result of 32-bit shift implicitly converted t…

…o 64 bits" warning. NFCI.
llvm · Sep 14, 2020 · 00e5676 · 00e5676
1 parent 687e1d7
commit 00e5676
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2800,7 +2800,7 @@ SDValue SelectionDAGLegalize::ExpandPARITY(SDValue Op, const SDLoc &dl) {
     Result = Op;
     for (unsigned i = Log2_32_Ceil(Sz); i != 0;) {
       SDValue Shift = DAG.getNode(ISD::SRL, dl, VT, Result,
-                                  DAG.getConstant(1 << (--i), dl, ShVT));
+                                  DAG.getConstant(1ULL << (--i), dl, ShVT));
       Result = DAG.getNode(ISD::XOR, dl, VT, Result, Shift);
     }
   }