-
Notifications
You must be signed in to change notification settings - Fork 11.6k
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
[DPWBS-1131] feat(RegisterBankSelect): add case for G_SHL, G_ASHR, G_…
…LSHR to getInstrMapping Allthough all legal cases are already inferred correctly in the default case of getInstrMapping, I decided to add them explicitly to the same-kind-of-operand handling. add regbankselect tests for all legal inputs
- Loading branch information
1 parent
0b0c50b
commit 0b94d2d
Showing
2 changed files
with
57 additions
and
0 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
53 changes: 53 additions & 0 deletions
53
llvm/test/CodeGen/TriCore/GlobalIsel/regbankselect-shifts.mir
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,53 @@ | ||
# RUN: llc -O0 -mtriple=tricore -global-isel -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s | ||
|
||
--- | ||
name: test_shl | ||
legalized: true | ||
registers: | ||
- { id: 0, class: _ } | ||
- { id: 1, class: _ } | ||
body: | | ||
bb.0: | ||
; CHECK-LABEL: name: test_shl | ||
; CHECK: [[D4:%[0-9]+]]:dataregbank(s32) = COPY $d4 | ||
; CHECK: [[D5:%[0-9]+]]:dataregbank(s32) = COPY $d5 | ||
; CHECK: [[SHL:%[0-9]+]]:dataregbank(s32) = G_SHL [[D4]], [[D5]] | ||
%0:_(s32) = COPY $d4 | ||
%1:_(s32) = COPY $d5 | ||
%2:_(s32) = G_SHL %0, %1 | ||
$d2 = COPY %2(s32) | ||
... | ||
--- | ||
name: test_lshr | ||
legalized: true | ||
registers: | ||
- { id: 0, class: _ } | ||
- { id: 1, class: _ } | ||
body: | | ||
bb.0: | ||
; CHECK-LABEL: name: test_lshr | ||
; CHECK: [[D4:%[0-9]+]]:dataregbank(s32) = COPY $d4 | ||
; CHECK: [[D5:%[0-9]+]]:dataregbank(s32) = COPY $d5 | ||
; CHECK: [[SHL:%[0-9]+]]:dataregbank(s32) = G_LSHR [[D4]], [[D5]] | ||
%0:_(s32) = COPY $d4 | ||
%1:_(s32) = COPY $d5 | ||
%2:_(s32) = G_LSHR %0, %1 | ||
$d2 = COPY %2(s32) | ||
... | ||
--- | ||
name: test_ashr | ||
legalized: true | ||
registers: | ||
- { id: 0, class: _ } | ||
- { id: 1, class: _ } | ||
body: | | ||
bb.0: | ||
; CHECK-LABEL: name: test_ashr | ||
; CHECK: [[D4:%[0-9]+]]:dataregbank(s32) = COPY $d4 | ||
; CHECK: [[D5:%[0-9]+]]:dataregbank(s32) = COPY $d5 | ||
; CHECK: [[SHL:%[0-9]+]]:dataregbank(s32) = G_ASHR [[D4]], [[D5]] | ||
%0:_(s32) = COPY $d4 | ||
%1:_(s32) = COPY $d5 | ||
%2:_(s32) = G_ASHR %0, %1 | ||
$d2 = COPY %2(s32) | ||
... |