AVX512: Change encoding of vpshuflw and vpshufhw instructions. Implem…

…ent WIG as W0 and not W1, like all other instruction have been implemented. Add encoding tests. Differential Revision: http://reviews.llvm.org/D13471 llvm-svn: 249521
llvm · Oct 7, 2015 · 1a6fd1c · 1a6fd1c
1 parent cea0b3b
commit 1a6fd1c
Show file tree

Hide file tree

Showing 3 changed files with 363 additions and 123 deletions.
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -1842,7 +1842,6 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
   }
 }
 
-
 multiclass avx512_vector_fpclass_all<string OpcodeStr,
             AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd, 
                                                               string broadcast>{
@@ -4149,9 +4148,9 @@ defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
                              X86PShufd, avx512vl_i32_info>,
                              EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
-                                  X86PShufhw>, EVEX, AVX512XSIi8Base, VEX_W;
+                                  X86PShufhw>, EVEX, AVX512XSIi8Base;
 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
-                                  X86PShuflw>, EVEX, AVX512XDIi8Base, VEX_W;
+                                  X86PShuflw>, EVEX, AVX512XDIi8Base;
 
 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
   let Predicates = [HasBWI] in

diff --git a/llvm/test/MC/X86/x86-64-avx512bw.s b/llvm/test/MC/X86/x86-64-avx512bw.s
@@ -4315,3 +4315,84 @@
 // CHECK: vpsadbw -8256(%rdx), %zmm25, %zmm28
 // CHECK:  encoding: [0x62,0x61,0x35,0x40,0xf6,0xa2,0xc0,0xdf,0xff,0xff]
           vpsadbw -8256(%rdx), %zmm25, %zmm28
+
+// CHECK: vpshuflw $171, %zmm28, %zmm26
+// CHECK:  encoding: [0x62,0x01,0x7f,0x48,0x70,0xd4,0xab]
+          vpshuflw $171, %zmm28, %zmm26
+
+// CHECK: vpshuflw $171, %zmm28, %zmm26 {%k1}
+// CHECK:  encoding: [0x62,0x01,0x7f,0x49,0x70,0xd4,0xab]
+          vpshuflw $171, %zmm28, %zmm26 {%k1}
+
+// CHECK: vpshuflw $171, %zmm28, %zmm26 {%k1} {z}
+// CHECK:  encoding: [0x62,0x01,0x7f,0xc9,0x70,0xd4,0xab]
+          vpshuflw $171, %zmm28, %zmm26 {%k1} {z}
+
+// CHECK: vpshuflw $123, %zmm28, %zmm26
+// CHECK:  encoding: [0x62,0x01,0x7f,0x48,0x70,0xd4,0x7b]
+          vpshuflw $123, %zmm28, %zmm26
+
+// CHECK: vpshuflw $123, (%rcx), %zmm26
+// CHECK:  encoding: [0x62,0x61,0x7f,0x48,0x70,0x11,0x7b]
+          vpshuflw $123, (%rcx), %zmm26
+
+// CHECK: vpshuflw $123, 291(%rax,%r14,8), %zmm26
+// CHECK:  encoding: [0x62,0x21,0x7f,0x48,0x70,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpshuflw $123, 291(%rax,%r14,8), %zmm26
+
+// CHECK: vpshuflw $123, 8128(%rdx), %zmm26
+// CHECK:  encoding: [0x62,0x61,0x7f,0x48,0x70,0x52,0x7f,0x7b]
+          vpshuflw $123, 8128(%rdx), %zmm26
+
+// CHECK: vpshuflw $123, 8192(%rdx), %zmm26
+// CHECK:  encoding: [0x62,0x61,0x7f,0x48,0x70,0x92,0x00,0x20,0x00,0x00,0x7b]
+          vpshuflw $123, 8192(%rdx), %zmm26
+
+// CHECK: vpshuflw $123, -8192(%rdx), %zmm26
+// CHECK:  encoding: [0x62,0x61,0x7f,0x48,0x70,0x52,0x80,0x7b]
+          vpshuflw $123, -8192(%rdx), %zmm26
+
+// CHECK: vpshuflw $123, -8256(%rdx), %zmm26
+// CHECK:  encoding: [0x62,0x61,0x7f,0x48,0x70,0x92,0xc0,0xdf,0xff,0xff,0x7b]
+          vpshuflw $123, -8256(%rdx), %zmm26
+
+// CHECK: vpshufhw $171, %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xa1,0x7e,0x48,0x70,0xd2,0xab]
+          vpshufhw $171, %zmm18, %zmm18
+
+// CHECK: vpshufhw $171, %zmm18, %zmm18 {%k4}
+// CHECK:  encoding: [0x62,0xa1,0x7e,0x4c,0x70,0xd2,0xab]
+          vpshufhw $171, %zmm18, %zmm18 {%k4}
+
+// CHECK: vpshufhw $171, %zmm18, %zmm18 {%k4} {z}
+// CHECK:  encoding: [0x62,0xa1,0x7e,0xcc,0x70,0xd2,0xab]
+          vpshufhw $171, %zmm18, %zmm18 {%k4} {z}
+
+// CHECK: vpshufhw $123, %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xa1,0x7e,0x48,0x70,0xd2,0x7b]
+          vpshufhw $123, %zmm18, %zmm18
+
+// CHECK: vpshufhw $123, (%rcx), %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x7e,0x48,0x70,0x11,0x7b]
+          vpshufhw $123, (%rcx), %zmm18
+
+// CHECK: vpshufhw $123, 291(%rax,%r14,8), %zmm18
+// CHECK:  encoding: [0x62,0xa1,0x7e,0x48,0x70,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpshufhw $123, 291(%rax,%r14,8), %zmm18
+
+// CHECK: vpshufhw $123, 8128(%rdx), %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x7e,0x48,0x70,0x52,0x7f,0x7b]
+          vpshufhw $123, 8128(%rdx), %zmm18
+
+// CHECK: vpshufhw $123, 8192(%rdx), %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x7e,0x48,0x70,0x92,0x00,0x20,0x00,0x00,0x7b]
+          vpshufhw $123, 8192(%rdx), %zmm18
+
+// CHECK: vpshufhw $123, -8192(%rdx), %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x7e,0x48,0x70,0x52,0x80,0x7b]
+          vpshufhw $123, -8192(%rdx), %zmm18
+
+// CHECK: vpshufhw $123, -8256(%rdx), %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x7e,0x48,0x70,0x92,0xc0,0xdf,0xff,0xff,0x7b]
+          vpshufhw $123, -8256(%rdx), %zmm18
+