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[PPC] Change the register constraint of the first source operand of i…
…nstruction mtvsrdd to g8rc_nox0 According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0. This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified. Differential Revision: https://reviews.llvm.org/D32880 llvm-svn: 302834
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,22 @@ | ||
; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \ | ||
; RUN: < %s | FileCheck %s | ||
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; This test case checks r0 is used as constant 0 in instruction mtvsrdd. | ||
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define <2 x i64> @const0(i64 %a) { | ||
%vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 | ||
%vecinit1 = insertelement <2 x i64> %vecinit, i64 0, i32 1 | ||
ret <2 x i64> %vecinit1 | ||
; CHECK-LABEL: const0 | ||
; CHECK: mtvsrdd v2, 0, r3 | ||
} | ||
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define <2 x i64> @noconst0(i64* %a, i64* %b) { | ||
%1 = load i64, i64* %a, align 8 | ||
%2 = load i64, i64* %b, align 8 | ||
%vecinit = insertelement <2 x i64> undef, i64 %2, i32 0 | ||
%vecinit1 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 | ||
ret <2 x i64> %vecinit1 | ||
; CHECK-LABEL: noconst0 | ||
; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}} | ||
} |
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llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-p9vector.txt
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@@ -0,0 +1,4 @@ | ||
# RUN: llvm-mc --disassemble %s -triple powerpc64le-unknown-unknown -mcpu=pwr9 | FileCheck %s | ||
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# CHECK: mtvsrdd 6, 0, 3 | ||
0x66 0x1b 0xc0 0x7c |