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[RISCV] Remove GetVRegNoV0 from the output register class of masked c…
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…ompare pseudo instructions.

Theses instructions are allowed to write v0 when they are masked.
We'll still never use v0 because of the earlyclobber constraint so
this doesn't really help anything. It just makes the definitions
correct.

While I was there remove an unused multiclass I noticed.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D101118
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@topperc
topperc committed Apr 23, 2021
1 parent fae1d31 commit 3064a63
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Showing 11 changed files with 87 additions and 69 deletions.
60 changes: 39 additions & 21 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Original file line number Diff line number Diff line change
Expand Up @@ -884,23 +884,6 @@ class VPseudoMaskUnarySOutMask:
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}

// Masked mask operation have no $rd=$merge constraints
class VPseudoUnaryMOutMask:
Pseudo<(outs VR:$rd),
(ins VR:$merge, VR:$rs1, VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let usesCustomInserter = 1;
let Constraints = "$rd = $merge";
let Uses = [VL, VTYPE];
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}

// Mask can be V0~V31
class VPseudoUnaryAnyMask<VReg RetClass,
VReg Op1Class> :
Expand Down Expand Up @@ -995,6 +978,28 @@ class VPseudoBinaryMask<VReg RetClass,
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}

// Like VPseudoBinaryMask, but output can be V0.
class VPseudoBinaryMOutMask<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
string Constraint> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let usesCustomInserter = 1;
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let Uses = [VL, VTYPE];
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}

class VPseudoBinaryCarryIn<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
Expand Down Expand Up @@ -1507,6 +1512,19 @@ multiclass VPseudoBinary<VReg RetClass,
}
}

multiclass VPseudoBinaryM<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = ""> {
let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
Op2Class, Constraint>;
}
}

multiclass VPseudoBinaryEmul<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
Expand Down Expand Up @@ -1740,25 +1758,25 @@ multiclass PseudoUnaryV_VF8 {
// @earlyclobber to avoid the overlap between destination and source registers.
multiclass VPseudoBinaryM_VV {
foreach m = MxList.m in
defm _VV : VPseudoBinary<VR, m.vrclass, m.vrclass, m, "@earlyclobber $rd">;
defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m, "@earlyclobber $rd">;
}

multiclass VPseudoBinaryM_VX {
foreach m = MxList.m in
defm "_VX" :
VPseudoBinary<VR, m.vrclass, GPR, m, "@earlyclobber $rd">;
VPseudoBinaryM<VR, m.vrclass, GPR, m, "@earlyclobber $rd">;
}

multiclass VPseudoBinaryM_VF {
foreach m = MxList.m in
foreach f = FPList.fpinfo in
defm "_V" # f.FX :
VPseudoBinary<VR, m.vrclass, f.fprclass, m, "@earlyclobber $rd">;
VPseudoBinaryM<VR, m.vrclass, f.fprclass, m, "@earlyclobber $rd">;
}

multiclass VPseudoBinaryM_VI {
foreach m = MxList.m in
defm _VI : VPseudoBinary<VR, m.vrclass, simm5, m, "@earlyclobber $rd">;
defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m, "@earlyclobber $rd">;
}

multiclass VPseudoBinaryV_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vv v26, v8, v25, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vmseq.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1713,12 +1713,12 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vv v26, v25, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
Expand Down Expand Up @@ -2761,11 +2761,11 @@ define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmsle.vv v26, v25, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1713,12 +1713,12 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vv v26, v25, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
Expand Down Expand Up @@ -2761,11 +2761,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmsleu.vv v26, v25, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vv v26, v25, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vmslt.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vv v26, v25, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vmsltu.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vv v26, v8, v25, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vmsle.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vv v26, v8, v25, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vmsleu.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vv v26, v8, v25, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vmslt.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vv v26, v8, v25, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vmsltu.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vv v26, v8, v25, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vmsne.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
Expand Down

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