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[SelectionDAG] Widen scalable-vector loads/stores via VP_LOAD/VP_STORE
This patch fixes a compiler crash when widening scalable-vector loads and stores which end up breaking down to element-wise store operations. It does so by providing a way for targets with support for vector-predicated loads and stores to use those instead. By widening the operation but maintaining the original effective operation length via the EVL, only the intended vector elements are loaded or stored. This method should in theory be possible and even preferred for fixed-length vector types, but all fixed-length types can be broken down into their elements, and regardless I have observed regressions in the generated code when doing so. I believe this is simply due to VP_LOAD/VP_STORE not being up to par with LOAD/STORE in terms of optimization. It does improve performance on smaller self-contained examples, however, so the potential is there. While the only target that benefits from this is RISCV, the legalization is generic and so was placed centrally. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D111248
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Original file line number | Diff line number | Diff line change |
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@@ -1,16 +1,33 @@ | ||
; RUN: not --crash llc -mtriple=riscv32 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | ||
; RUN: not --crash llc -mtriple=riscv64 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | ||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | ||
; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s | ||
; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s | ||
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; Check that we are able to legalize scalable-vector loads that require widening. | ||
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; FIXME: LLVM can't yet widen scalable-vector loads. | ||
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define <vscale x 3 x i8> @load_nxv3i8(<vscale x 3 x i8>* %ptr) { | ||
; CHECK-LABEL: load_nxv3i8: | ||
; CHECK: # %bb.0: | ||
; CHECK-NEXT: csrr a1, vlenb | ||
; CHECK-NEXT: srli a1, a1, 3 | ||
; CHECK-NEXT: slli a2, a1, 1 | ||
; CHECK-NEXT: add a1, a2, a1 | ||
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu | ||
; CHECK-NEXT: vle8.v v8, (a0) | ||
; CHECK-NEXT: ret | ||
%v = load <vscale x 3 x i8>, <vscale x 3 x i8>* %ptr | ||
ret <vscale x 3 x i8> %v | ||
} | ||
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define <vscale x 5 x half> @load_nxv5f16(<vscale x 5 x half>* %ptr) { | ||
; CHECK-LABEL: load_nxv5f16: | ||
; CHECK: # %bb.0: | ||
; CHECK-NEXT: csrr a1, vlenb | ||
; CHECK-NEXT: srli a1, a1, 3 | ||
; CHECK-NEXT: slli a2, a1, 2 | ||
; CHECK-NEXT: add a1, a2, a1 | ||
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu | ||
; CHECK-NEXT: vle16.v v8, (a0) | ||
; CHECK-NEXT: ret | ||
%v = load <vscale x 5 x half>, <vscale x 5 x half>* %ptr | ||
ret <vscale x 5 x half> %v | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,16 +1,33 @@ | ||
; RUN: not --crash llc -mtriple=riscv32 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | ||
; RUN: not --crash llc -mtriple=riscv64 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | ||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | ||
; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s | ||
; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s | ||
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; Check that we are able to legalize scalable-vector stores that require widening. | ||
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; FIXME: LLVM can't yet widen scalable-vector stores. | ||
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define void @store_nxv3i8(<vscale x 3 x i8> %val, <vscale x 3 x i8>* %ptr) { | ||
; CHECK-LABEL: store_nxv3i8: | ||
; CHECK: # %bb.0: | ||
; CHECK-NEXT: csrr a1, vlenb | ||
; CHECK-NEXT: srli a1, a1, 3 | ||
; CHECK-NEXT: slli a2, a1, 1 | ||
; CHECK-NEXT: add a1, a2, a1 | ||
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu | ||
; CHECK-NEXT: vse8.v v8, (a0) | ||
; CHECK-NEXT: ret | ||
store <vscale x 3 x i8> %val, <vscale x 3 x i8>* %ptr | ||
ret void | ||
} | ||
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define void @store_nxv7f64(<vscale x 7 x double> %val, <vscale x 7 x double>* %ptr) { | ||
; CHECK-LABEL: store_nxv7f64: | ||
; CHECK: # %bb.0: | ||
; CHECK-NEXT: csrr a1, vlenb | ||
; CHECK-NEXT: srli a1, a1, 3 | ||
; CHECK-NEXT: slli a2, a1, 3 | ||
; CHECK-NEXT: sub a1, a2, a1 | ||
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu | ||
; CHECK-NEXT: vse64.v v8, (a0) | ||
; CHECK-NEXT: ret | ||
store <vscale x 7 x double> %val, <vscale x 7 x double>* %ptr | ||
ret void | ||
} |