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[RISCV] Define vector mask-register logical intrinsics.
Define vector mask-register logical intrinsics and lower them to V instructions. Also define pseudo instructions vmmv.m and vmnot.m. We work with @rogfer01 from BSC to come out this patch. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Differential Revision: https://reviews.llvm.org/D93705
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ | ||
; RUN: --riscv-no-aliases < %s | FileCheck %s | ||
declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1( | ||
<vscale x 1 x i1>, | ||
<vscale x 1 x i1>, | ||
i32); | ||
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define <vscale x 1 x i1> @intrinsic_vmand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1( | ||
<vscale x 1 x i1> %0, | ||
<vscale x 1 x i1> %1, | ||
i32 %2) | ||
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ret <vscale x 1 x i1> %a | ||
} | ||
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declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1( | ||
<vscale x 2 x i1>, | ||
<vscale x 2 x i1>, | ||
i32); | ||
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||
define <vscale x 2 x i1> @intrinsic_vmand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1( | ||
<vscale x 2 x i1> %0, | ||
<vscale x 2 x i1> %1, | ||
i32 %2) | ||
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ret <vscale x 2 x i1> %a | ||
} | ||
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declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1( | ||
<vscale x 4 x i1>, | ||
<vscale x 4 x i1>, | ||
i32); | ||
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define <vscale x 4 x i1> @intrinsic_vmand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1( | ||
<vscale x 4 x i1> %0, | ||
<vscale x 4 x i1> %1, | ||
i32 %2) | ||
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ret <vscale x 4 x i1> %a | ||
} | ||
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declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1( | ||
<vscale x 8 x i1>, | ||
<vscale x 8 x i1>, | ||
i32); | ||
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define <vscale x 8 x i1> @intrinsic_vmand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv8i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1( | ||
<vscale x 8 x i1> %0, | ||
<vscale x 8 x i1> %1, | ||
i32 %2) | ||
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ret <vscale x 8 x i1> %a | ||
} | ||
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declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1( | ||
<vscale x 16 x i1>, | ||
<vscale x 16 x i1>, | ||
i32); | ||
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define <vscale x 16 x i1> @intrinsic_vmand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv16i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1( | ||
<vscale x 16 x i1> %0, | ||
<vscale x 16 x i1> %1, | ||
i32 %2) | ||
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ret <vscale x 16 x i1> %a | ||
} | ||
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declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1( | ||
<vscale x 32 x i1>, | ||
<vscale x 32 x i1>, | ||
i32); | ||
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define <vscale x 32 x i1> @intrinsic_vmand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv32i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1( | ||
<vscale x 32 x i1> %0, | ||
<vscale x 32 x i1> %1, | ||
i32 %2) | ||
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ret <vscale x 32 x i1> %a | ||
} | ||
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declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1( | ||
<vscale x 64 x i1>, | ||
<vscale x 64 x i1>, | ||
i32); | ||
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define <vscale x 64 x i1> @intrinsic_vmand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv64i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1( | ||
<vscale x 64 x i1> %0, | ||
<vscale x 64 x i1> %1, | ||
i32 %2) | ||
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ret <vscale x 64 x i1> %a | ||
} |
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@@ -0,0 +1,127 @@ | ||
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ | ||
; RUN: --riscv-no-aliases < %s | FileCheck %s | ||
declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1( | ||
<vscale x 1 x i1>, | ||
<vscale x 1 x i1>, | ||
i64); | ||
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||
define <vscale x 1 x i1> @intrinsic_vmand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1( | ||
<vscale x 1 x i1> %0, | ||
<vscale x 1 x i1> %1, | ||
i64 %2) | ||
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ret <vscale x 1 x i1> %a | ||
} | ||
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declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1( | ||
<vscale x 2 x i1>, | ||
<vscale x 2 x i1>, | ||
i64); | ||
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define <vscale x 2 x i1> @intrinsic_vmand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1( | ||
<vscale x 2 x i1> %0, | ||
<vscale x 2 x i1> %1, | ||
i64 %2) | ||
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ret <vscale x 2 x i1> %a | ||
} | ||
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declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1( | ||
<vscale x 4 x i1>, | ||
<vscale x 4 x i1>, | ||
i64); | ||
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define <vscale x 4 x i1> @intrinsic_vmand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1( | ||
<vscale x 4 x i1> %0, | ||
<vscale x 4 x i1> %1, | ||
i64 %2) | ||
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ret <vscale x 4 x i1> %a | ||
} | ||
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declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1( | ||
<vscale x 8 x i1>, | ||
<vscale x 8 x i1>, | ||
i64); | ||
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define <vscale x 8 x i1> @intrinsic_vmand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv8i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1( | ||
<vscale x 8 x i1> %0, | ||
<vscale x 8 x i1> %1, | ||
i64 %2) | ||
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ret <vscale x 8 x i1> %a | ||
} | ||
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declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1( | ||
<vscale x 16 x i1>, | ||
<vscale x 16 x i1>, | ||
i64); | ||
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define <vscale x 16 x i1> @intrinsic_vmand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv16i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1( | ||
<vscale x 16 x i1> %0, | ||
<vscale x 16 x i1> %1, | ||
i64 %2) | ||
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ret <vscale x 16 x i1> %a | ||
} | ||
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declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1( | ||
<vscale x 32 x i1>, | ||
<vscale x 32 x i1>, | ||
i64); | ||
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define <vscale x 32 x i1> @intrinsic_vmand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv32i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1( | ||
<vscale x 32 x i1> %0, | ||
<vscale x 32 x i1> %1, | ||
i64 %2) | ||
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ret <vscale x 32 x i1> %a | ||
} | ||
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declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1( | ||
<vscale x 64 x i1>, | ||
<vscale x 64 x i1>, | ||
i64); | ||
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define <vscale x 64 x i1> @intrinsic_vmand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind { | ||
entry: | ||
; CHECK-LABEL: intrinsic_vmand_mm_nxv64i1 | ||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu | ||
; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} | ||
%a = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1( | ||
<vscale x 64 x i1> %0, | ||
<vscale x 64 x i1> %1, | ||
i64 %2) | ||
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ret <vscale x 64 x i1> %a | ||
} |
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