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[RISCV] Fix crash with fptosi.sat/fptoui.sat intrinsics on RV64. Add …
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…test cases.

Add PromoteIntOp_FP_TO_XINT_SAT to type legalize the bit width
operand from i32 to i64 for RV64.

Add test cases for the saturating intrinsics for half/float/double
and i32/i64. CodeGen is definitely not optimal. We can probably
make use of the native behavior of fcvt instructions in many cases.

Fixes PR50083
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@topperc
topperc committed Apr 22, 2021
1 parent 06234f7 commit 5185b52
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9 changes: 9 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1547,6 +1547,9 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {

case ISD::FPOWI: Res = PromoteIntOp_FPOWI(N); break;

case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT: PromoteIntOp_FP_TO_XINT_SAT(N); break;

case ISD::VECREDUCE_ADD:
case ISD::VECREDUCE_MUL:
case ISD::VECREDUCE_AND:
Expand Down Expand Up @@ -1967,6 +1970,12 @@ SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), Op2), 0);
}

SDValue DAGTypeLegalizer::PromoteIntOp_FP_TO_XINT_SAT(SDNode *N) {
SDValue Op1 = ZExtPromotedInteger(N->getOperand(1));
return SDValue(
DAG.UpdateNodeOperands(N, N->getOperand(0), Op1), 0);
}

SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
// Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
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1 change: 1 addition & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
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Original file line number Diff line number Diff line change
Expand Up @@ -391,6 +391,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntOp_FRAMERETURNADDR(SDNode *N);
SDValue PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_FIX(SDNode *N);
SDValue PromoteIntOp_FP_TO_XINT_SAT(SDNode *N);
SDValue PromoteIntOp_FPOWI(SDNode *N);
SDValue PromoteIntOp_VECREDUCE(SDNode *N);
SDValue PromoteIntOp_SET_ROUNDING(SDNode *N);
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241 changes: 241 additions & 0 deletions llvm/test/CodeGen/RISCV/double-convert.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -70,6 +70,53 @@ define i32 @fcvt_w_d(double %a) nounwind {
ret i32 %1
}

define i32 @fcvt_w_d_sat(double %a) nounwind {
; RV32IFD-LABEL: fcvt_w_d_sat:
; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft0, ft0
; RV32IFD-NEXT: bnez a0, .LBB3_2
; RV32IFD-NEXT: # %bb.1: # %start
; RV32IFD-NEXT: mv a0, zero
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB3_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI3_0)
; RV32IFD-NEXT: fld ft1, %lo(.LCPI3_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI3_1)
; RV32IFD-NEXT: fld ft2, %lo(.LCPI3_1)(a0)
; RV32IFD-NEXT: fmax.d ft0, ft0, ft1
; RV32IFD-NEXT: fmin.d ft0, ft0, ft2
; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_w_d_sat:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0
; RV64IFD-NEXT: bnez a0, .LBB3_2
; RV64IFD-NEXT: # %bb.1: # %start
; RV64IFD-NEXT: mv a0, zero
; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB3_2:
; RV64IFD-NEXT: lui a0, %hi(.LCPI3_0)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI3_0)(a0)
; RV64IFD-NEXT: lui a0, %hi(.LCPI3_1)
; RV64IFD-NEXT: fld ft2, %lo(.LCPI3_1)(a0)
; RV64IFD-NEXT: fmax.d ft0, ft0, ft1
; RV64IFD-NEXT: fmin.d ft0, ft0, ft2
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
; RV64IFD-NEXT: ret
start:
%0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
ret i32 %0
}
declare i32 @llvm.fptosi.sat.i32.f64(double)

; For RV64D, fcvt.lu.d is semantically equivalent to fcvt.wu.d in this case
; because fptosi will produce poison if the result doesn't fit into an i32.
define i32 @fcvt_wu_d(double %a) nounwind {
Expand All @@ -92,6 +139,38 @@ define i32 @fcvt_wu_d(double %a) nounwind {
ret i32 %1
}

define i32 @fcvt_wu_d_sat(double %a) nounwind {
; RV32IFD-LABEL: fcvt_wu_d_sat:
; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: lui a0, %hi(.LCPI5_0)
; RV32IFD-NEXT: fld ft1, %lo(.LCPI5_0)(a0)
; RV32IFD-NEXT: fcvt.d.w ft2, zero
; RV32IFD-NEXT: fmax.d ft0, ft0, ft2
; RV32IFD-NEXT: fmin.d ft0, ft0, ft1
; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_wu_d_sat:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: lui a1, %hi(.LCPI5_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI5_0)(a1)
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fmv.d.x ft2, zero
; RV64IFD-NEXT: fmax.d ft1, ft1, ft2
; RV64IFD-NEXT: fmin.d ft0, ft1, ft0
; RV64IFD-NEXT: fcvt.lu.d a0, ft0, rtz
; RV64IFD-NEXT: ret
start:
%0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a)
ret i32 %0
}
declare i32 @llvm.fptoui.sat.i32.f64(double)

define double @fcvt_d_w(i32 %a) nounwind {
; RV32IFD-LABEL: fcvt_d_w:
; RV32IFD: # %bb.0:
Expand Down Expand Up @@ -151,6 +230,98 @@ define i64 @fcvt_l_d(double %a) nounwind {
ret i64 %1
}

define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32IFD-LABEL: fcvt_l_d_sat:
; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: lui a2, %hi(.LCPI9_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI9_0)(a2)
; RV32IFD-NEXT: fle.d a3, ft0, ft1
; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez a3, .LBB9_2
; RV32IFD-NEXT: # %bb.1: # %start
; RV32IFD-NEXT: mv a2, zero
; RV32IFD-NEXT: .LBB9_2: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI9_1)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI9_1)(a0)
; RV32IFD-NEXT: flt.d a4, ft0, ft1
; RV32IFD-NEXT: addi a0, zero, -1
; RV32IFD-NEXT: beqz a4, .LBB9_9
; RV32IFD-NEXT: # %bb.3: # %start
; RV32IFD-NEXT: feq.d a2, ft1, ft1
; RV32IFD-NEXT: beqz a2, .LBB9_10
; RV32IFD-NEXT: .LBB9_4: # %start
; RV32IFD-NEXT: lui a5, 524288
; RV32IFD-NEXT: beqz a3, .LBB9_11
; RV32IFD-NEXT: .LBB9_5: # %start
; RV32IFD-NEXT: bnez a4, .LBB9_12
; RV32IFD-NEXT: .LBB9_6: # %start
; RV32IFD-NEXT: bnez a2, .LBB9_8
; RV32IFD-NEXT: .LBB9_7: # %start
; RV32IFD-NEXT: mv a1, zero
; RV32IFD-NEXT: .LBB9_8: # %start
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB9_9: # %start
; RV32IFD-NEXT: mv a0, a2
; RV32IFD-NEXT: feq.d a2, ft1, ft1
; RV32IFD-NEXT: bnez a2, .LBB9_4
; RV32IFD-NEXT: .LBB9_10: # %start
; RV32IFD-NEXT: mv a0, zero
; RV32IFD-NEXT: lui a5, 524288
; RV32IFD-NEXT: bnez a3, .LBB9_5
; RV32IFD-NEXT: .LBB9_11: # %start
; RV32IFD-NEXT: lui a1, 524288
; RV32IFD-NEXT: beqz a4, .LBB9_6
; RV32IFD-NEXT: .LBB9_12:
; RV32IFD-NEXT: addi a1, a5, -1
; RV32IFD-NEXT: beqz a2, .LBB9_7
; RV32IFD-NEXT: j .LBB9_8
;
; RV64IFD-LABEL: fcvt_l_d_sat:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: lui a1, %hi(.LCPI9_0)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI9_0)(a1)
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: addi a1, zero, -1
; RV64IFD-NEXT: bnez a0, .LBB9_2
; RV64IFD-NEXT: # %bb.1: # %start
; RV64IFD-NEXT: slli a0, a1, 63
; RV64IFD-NEXT: j .LBB9_3
; RV64IFD-NEXT: .LBB9_2:
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
; RV64IFD-NEXT: .LBB9_3: # %start
; RV64IFD-NEXT: lui a2, %hi(.LCPI9_1)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI9_1)(a2)
; RV64IFD-NEXT: flt.d a2, ft1, ft0
; RV64IFD-NEXT: bnez a2, .LBB9_6
; RV64IFD-NEXT: # %bb.4: # %start
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: beqz a1, .LBB9_7
; RV64IFD-NEXT: .LBB9_5: # %start
; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB9_6:
; RV64IFD-NEXT: srli a0, a1, 1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: bnez a1, .LBB9_5
; RV64IFD-NEXT: .LBB9_7: # %start
; RV64IFD-NEXT: mv a0, zero
; RV64IFD-NEXT: ret
start:
%0 = tail call i64 @llvm.fptosi.sat.i64.f64(double %a)
ret i64 %0
}
declare i64 @llvm.fptosi.sat.i64.f64(double)

define i64 @fcvt_lu_d(double %a) nounwind {
; RV32IFD-LABEL: fcvt_lu_d:
; RV32IFD: # %bb.0:
Expand All @@ -170,6 +341,76 @@ define i64 @fcvt_lu_d(double %a) nounwind {
ret i64 %1
}

define i64 @fcvt_lu_d_sat(double %a) nounwind {
; RV32IFD-LABEL: fcvt_lu_d_sat:
; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: fcvt.d.w ft0, zero
; RV32IFD-NEXT: fle.d a4, ft0, ft1
; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez a4, .LBB11_2
; RV32IFD-NEXT: # %bb.1: # %start
; RV32IFD-NEXT: mv a3, zero
; RV32IFD-NEXT: .LBB11_2: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI11_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI11_0)(a0)
; RV32IFD-NEXT: flt.d a5, ft0, ft1
; RV32IFD-NEXT: addi a2, zero, -1
; RV32IFD-NEXT: addi a0, zero, -1
; RV32IFD-NEXT: beqz a5, .LBB11_7
; RV32IFD-NEXT: # %bb.3: # %start
; RV32IFD-NEXT: beqz a4, .LBB11_8
; RV32IFD-NEXT: .LBB11_4: # %start
; RV32IFD-NEXT: bnez a5, .LBB11_6
; RV32IFD-NEXT: .LBB11_5: # %start
; RV32IFD-NEXT: mv a2, a1
; RV32IFD-NEXT: .LBB11_6: # %start
; RV32IFD-NEXT: mv a1, a2
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB11_7: # %start
; RV32IFD-NEXT: mv a0, a3
; RV32IFD-NEXT: bnez a4, .LBB11_4
; RV32IFD-NEXT: .LBB11_8: # %start
; RV32IFD-NEXT: mv a1, zero
; RV32IFD-NEXT: beqz a5, .LBB11_5
; RV32IFD-NEXT: j .LBB11_6
;
; RV64IFD-LABEL: fcvt_lu_d_sat:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, zero
; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: bnez a0, .LBB11_2
; RV64IFD-NEXT: # %bb.1: # %start
; RV64IFD-NEXT: mv a1, zero
; RV64IFD-NEXT: j .LBB11_3
; RV64IFD-NEXT: .LBB11_2:
; RV64IFD-NEXT: fcvt.lu.d a1, ft0, rtz
; RV64IFD-NEXT: .LBB11_3: # %start
; RV64IFD-NEXT: lui a0, %hi(.LCPI11_0)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI11_0)(a0)
; RV64IFD-NEXT: flt.d a2, ft1, ft0
; RV64IFD-NEXT: addi a0, zero, -1
; RV64IFD-NEXT: bnez a2, .LBB11_5
; RV64IFD-NEXT: # %bb.4: # %start
; RV64IFD-NEXT: mv a0, a1
; RV64IFD-NEXT: .LBB11_5: # %start
; RV64IFD-NEXT: ret
start:
%0 = tail call i64 @llvm.fptoui.sat.i64.f64(double %a)
ret i64 %0
}
declare i64 @llvm.fptoui.sat.i64.f64(double)

define i64 @fmv_x_d(double %a, double %b) nounwind {
; RV32IFD-LABEL: fmv_x_d:
; RV32IFD: # %bb.0:
Expand Down
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