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[AArch64][SVE] Match (add x (lsr/asr y c)) -> usra/ssra x y c
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Differential Revision: https://reviews.llvm.org/D128045
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@brads55
brads55 committed Jun 23, 2022
1 parent 79e77a9 commit 6f27df5
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10 changes: 10 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
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Expand Up @@ -240,6 +240,16 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
return SelectSVEShiftImm(N, Low, High, AllowSaturation, Imm);
}

bool SelectSVEShiftSplatImmR(SDValue N, SDValue &Imm) {
if (N->getOpcode() != ISD::SPLAT_VECTOR)
return false;

EVT EltVT = N->getValueType(0).getVectorElementType();
return SelectSVEShiftImm(N->getOperand(0), /* Low */ 1,
/* High */ EltVT.getFixedSizeInBits(),
/* AllowSaturation */ true, Imm);
}

// Returns a suitable CNT/INC/DEC/RDVL multiplier to calculate VSCALE*N.
template<signed Min, signed Max, signed Scale, bool Shift>
bool SelectCntImm(SDValue N, SDValue &Imm) {
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12 changes: 10 additions & 2 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Expand Up @@ -252,6 +252,14 @@ def AArch64uaba : PatFrags<(ops node:$op1, node:$op2, node:$op3),
[(int_aarch64_sve_uaba node:$op1, node:$op2, node:$op3),
(add node:$op1, (AArch64uabd_p (SVEAllActive), node:$op2, node:$op3))]>;

def AArch64usra : PatFrags<(ops node:$op1, node:$op2, node:$op3),
[(int_aarch64_sve_usra node:$op1, node:$op2, node:$op3),
(add node:$op1, (AArch64lsr_p (SVEAllActive), node:$op2, (SVEShiftSplatImmR (i32 node:$op3))))]>;

def AArch64ssra : PatFrags<(ops node:$op1, node:$op2, node:$op3),
[(int_aarch64_sve_ssra node:$op1, node:$op2, node:$op3),
(add node:$op1, (AArch64asr_p (SVEAllActive), node:$op2, (SVEShiftSplatImmR (i32 node:$op3))))]>;

def SDT_AArch64FCVT : SDTypeProfile<1, 3, [
SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3>,
SDTCVecEltisVT<1,i1>
Expand Down Expand Up @@ -3151,8 +3159,8 @@ let Predicates = [HasSVE2orSME] in {
defm SLI_ZZI : sve2_int_bin_shift_imm_left< 0b1, "sli", int_aarch64_sve_sli>;

// SVE2 bitwise shift right and accumulate
defm SSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b00, "ssra", int_aarch64_sve_ssra>;
defm USRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b01, "usra", int_aarch64_sve_usra>;
defm SSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b00, "ssra", AArch64ssra>;
defm USRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b01, "usra", AArch64usra>;
defm SRSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b10, "srsra", int_aarch64_sve_srsra>;
defm URSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b11, "ursra", int_aarch64_sve_ursra>;

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2 changes: 2 additions & 0 deletions llvm/lib/Target/AArch64/SVEInstrFormats.td
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Expand Up @@ -231,6 +231,8 @@ def SVEShiftImmR16 : ComplexPattern<i32, 1, "SelectSVEShiftImm<1, 16, true>", []
def SVEShiftImmR32 : ComplexPattern<i32, 1, "SelectSVEShiftImm<1, 32, true>", []>;
def SVEShiftImmR64 : ComplexPattern<i64, 1, "SelectSVEShiftImm<1, 64, true>", []>;

def SVEShiftSplatImmR : ComplexPattern<iAny, 1, "SelectSVEShiftSplatImmR", []>;

def SVEAllActive : ComplexPattern<untyped, 0, "SelectAllActivePredicate", []>;

class SVEExactFPImm<string Suffix, string ValA, string ValB> : AsmOperandClass {
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226 changes: 226 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2-sra.ll
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@@ -0,0 +1,226 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

; USRA

define <vscale x 16 x i8> @usra_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: usra_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: usra z0.b, z1.b, #1
; CHECK-NEXT: ret
%ins = insertelement <vscale x 16 x i8> poison, i8 1, i32 0
%splat = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
%shift = lshr <vscale x 16 x i8> %b, %splat
%add = add <vscale x 16 x i8> %a, %shift
ret <vscale x 16 x i8> %add
}

define <vscale x 8 x i16> @usra_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
; CHECK-LABEL: usra_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: usra z0.h, z1.h, #2
; CHECK-NEXT: ret
%ins = insertelement <vscale x 8 x i16> poison, i16 2, i32 0
%splat = shufflevector <vscale x 8 x i16> %ins, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
%shift = lshr <vscale x 8 x i16> %b, %splat
%add = add <vscale x 8 x i16> %a, %shift
ret <vscale x 8 x i16> %add
}

define <vscale x 4 x i32> @usra_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
; CHECK-LABEL: usra_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: usra z0.s, z1.s, #3
; CHECK-NEXT: ret
%ins = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %ins, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%shift = lshr <vscale x 4 x i32> %b, %splat
%add = add <vscale x 4 x i32> %a, %shift
ret <vscale x 4 x i32> %add
}

define <vscale x 2 x i64> @usra_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
; CHECK-LABEL: usra_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: usra z0.d, z1.d, #4
; CHECK-NEXT: ret
%ins = insertelement <vscale x 2 x i64> poison, i64 4, i32 0
%splat = shufflevector <vscale x 2 x i64> %ins, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%shift = lshr <vscale x 2 x i64> %b, %splat
%add = add <vscale x 2 x i64> %a, %shift
ret <vscale x 2 x i64> %add
}

define <vscale x 16 x i8> @usra_intr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: usra_intr_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: usra z0.b, z1.b, #1
; CHECK-NEXT: ret
%pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
%ins = insertelement <vscale x 16 x i8> poison, i8 1, i32 0
%splat = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
%shift = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %b, <vscale x 16 x i8> %splat)
%add = add <vscale x 16 x i8> %a, %shift
ret <vscale x 16 x i8> %add
}

define <vscale x 8 x i16> @usra_intr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
; CHECK-LABEL: usra_intr_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: usra z0.h, z1.h, #2
; CHECK-NEXT: ret
%pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%ins = insertelement <vscale x 8 x i16> poison, i16 2, i32 0
%splat = shufflevector <vscale x 8 x i16> %ins, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
%shift = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %b, <vscale x 8 x i16> %splat)
%add = add <vscale x 8 x i16> %a, %shift
ret <vscale x 8 x i16> %add
}

define <vscale x 4 x i32> @usra_intr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
; CHECK-LABEL: usra_intr_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: usra z0.s, z1.s, #3
; CHECK-NEXT: ret
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
%ins = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %ins, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%shift = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %b, <vscale x 4 x i32> %splat)
%add = add <vscale x 4 x i32> %a, %shift
ret <vscale x 4 x i32> %add
}

define <vscale x 2 x i64> @usra_intr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
; CHECK-LABEL: usra_intr_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: usra z0.d, z1.d, #4
; CHECK-NEXT: ret
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
%ins = insertelement <vscale x 2 x i64> poison, i64 4, i32 0
%splat = shufflevector <vscale x 2 x i64> %ins, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%shift = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %b, <vscale x 2 x i64> %splat)
%add = add <vscale x 2 x i64> %a, %shift
ret <vscale x 2 x i64> %add
}

; SSRA

define <vscale x 16 x i8> @ssra_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: ssra_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ssra z0.b, z1.b, #1
; CHECK-NEXT: ret
%ins = insertelement <vscale x 16 x i8> poison, i8 1, i32 0
%splat = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
%shift = ashr <vscale x 16 x i8> %b, %splat
%add = add <vscale x 16 x i8> %a, %shift
ret <vscale x 16 x i8> %add
}

define <vscale x 8 x i16> @ssra_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
; CHECK-LABEL: ssra_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ssra z0.h, z1.h, #2
; CHECK-NEXT: ret
%ins = insertelement <vscale x 8 x i16> poison, i16 2, i32 0
%splat = shufflevector <vscale x 8 x i16> %ins, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
%shift = ashr <vscale x 8 x i16> %b, %splat
%add = add <vscale x 8 x i16> %a, %shift
ret <vscale x 8 x i16> %add
}

define <vscale x 4 x i32> @ssra_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
; CHECK-LABEL: ssra_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ssra z0.s, z1.s, #3
; CHECK-NEXT: ret
%ins = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %ins, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%shift = ashr <vscale x 4 x i32> %b, %splat
%add = add <vscale x 4 x i32> %a, %shift
ret <vscale x 4 x i32> %add
}

define <vscale x 2 x i64> @ssra_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
; CHECK-LABEL: ssra_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ssra z0.d, z1.d, #4
; CHECK-NEXT: ret
%ins = insertelement <vscale x 2 x i64> poison, i64 4, i32 0
%splat = shufflevector <vscale x 2 x i64> %ins, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%shift = ashr <vscale x 2 x i64> %b, %splat
%add = add <vscale x 2 x i64> %a, %shift
ret <vscale x 2 x i64> %add
}

define <vscale x 16 x i8> @ssra_intr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: ssra_intr_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ssra z0.b, z1.b, #1
; CHECK-NEXT: ret
%pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
%ins = insertelement <vscale x 16 x i8> poison, i8 1, i32 0
%splat = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
%shift = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %b, <vscale x 16 x i8> %splat)
%add = add <vscale x 16 x i8> %a, %shift
ret <vscale x 16 x i8> %add
}

define <vscale x 8 x i16> @ssra_intr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
; CHECK-LABEL: ssra_intr_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ssra z0.h, z1.h, #2
; CHECK-NEXT: ret
%pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%ins = insertelement <vscale x 8 x i16> poison, i16 2, i32 0
%splat = shufflevector <vscale x 8 x i16> %ins, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
%shift = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %b, <vscale x 8 x i16> %splat)
%add = add <vscale x 8 x i16> %a, %shift
ret <vscale x 8 x i16> %add
}

define <vscale x 4 x i32> @ssra_intr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
; CHECK-LABEL: ssra_intr_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ssra z0.s, z1.s, #3
; CHECK-NEXT: ret
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
%ins = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %ins, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%shift = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %b, <vscale x 4 x i32> %splat)
%add = add <vscale x 4 x i32> %a, %shift
ret <vscale x 4 x i32> %add
}

define <vscale x 2 x i64> @ssra_intr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
; CHECK-LABEL: ssra_intr_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ssra z0.d, z1.d, #4
; CHECK-NEXT: ret
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
%ins = insertelement <vscale x 2 x i64> poison, i64 4, i32 0
%splat = shufflevector <vscale x 2 x i64> %ins, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%shift = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %b, <vscale x 2 x i64> %splat)
%add = add <vscale x 2 x i64> %a, %shift
ret <vscale x 2 x i64> %add
}


declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg)
declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg)
declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg)
declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 immarg)

declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)

declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)

attributes #0 = { "target-features"="+sve,+sve2" }

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