[X86][SSE] Add testnzc(~X,Y) -> testnzc(X,Y) test cases

llvm · Mar 28, 2020 · 8c1dbd5 · 8c1dbd5
1 parent d34d2ec
commit 8c1dbd5
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diff --git a/llvm/test/CodeGen/X86/combine-ptest.ll b/llvm/test/CodeGen/X86/combine-ptest.ll
@@ -1,6 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
 
+;
+; testz(~X,-1) -> testc(X,-1)
+;
+
 define i32 @ptestz_128_invert(<2 x i64> %c, i32 %a, i32 %b) {
 ; CHECK-LABEL: ptestz_128_invert:
 ; CHECK:       # %bb.0:
@@ -35,6 +39,10 @@ define i32 @ptestz_256_invert(<4 x i64> %c, i32 %a, i32 %b) {
   ret i32 %t4
 }
 
+;
+; testc(~X,-1) -> testz(X,-1)
+;
+
 define i32 @ptestc_128_invert(<2 x i64> %c, i32 %a, i32 %b) {
 ; CHECK-LABEL: ptestc_128_invert:
 ; CHECK:       # %bb.0:
@@ -69,6 +77,10 @@ define i32 @ptestc_256_invert(<4 x i64> %c, i32 %a, i32 %b) {
   ret i32 %t4
 }
 
+;
+; testnzc(~X,-1) -> testnzc(X,-1)
+;
+
 define i32 @ptestnzc_128_invert(<2 x i64> %c, i32 %a, i32 %b) {
 ; CHECK-LABEL: ptestnzc_128_invert:
 ; CHECK:       # %bb.0:
@@ -103,6 +115,44 @@ define i32 @ptestnzc_256_invert(<4 x i64> %c, i32 %a, i32 %b) {
   ret i32 %t4
 }
 
+;
+; testnzc(~X,Y) -> testnzc(X,Y)
+;
+
+define i32 @ptestnzc_128_flip(<2 x i64> %c, <2 x i64> %d, i32 %a, i32 %b) {
+; CHECK-LABEL: ptestnzc_128_flip:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vpxor %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vptest %xmm1, %xmm0
+; CHECK-NEXT:    cmovael %esi, %eax
+; CHECK-NEXT:    retq
+  %t1 = xor <2 x i64> %c, <i64 -1, i64 -1>
+  %t2 = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %t1, <2 x i64> %d)
+  %t3 = icmp ne i32 %t2, 0
+  %t4 = select i1 %t3, i32 %a, i32 %b
+  ret i32 %t4
+}
+
+define i32 @ptestnzc_256_flip(<4 x i64> %c, <4 x i64> %d, i32 %a, i32 %b) {
+; CHECK-LABEL: ptestnzc_256_flip:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vcmptrueps %ymm2, %ymm2, %ymm2
+; CHECK-NEXT:    vxorps %ymm2, %ymm0, %ymm0
+; CHECK-NEXT:    vptest %ymm1, %ymm0
+; CHECK-NEXT:    cmovbel %esi, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+  %t1 = xor <4 x i64> %c, <i64 -1, i64 -1, i64 -1, i64 -1>
+  %t2 = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %t1, <4 x i64> %d)
+  %t3 = icmp ne i32 %t2, 0
+  %t4 = select i1 %t3, i32 %a, i32 %b
+  ret i32 %t4
+}
+
 define zeroext i1 @PR38522(<16 x i8>* %x, <16 x i8>* %y) {
 ; CHECK-LABEL: PR38522:
 ; CHECK:       # %bb.0: # %start

diff --git a/llvm/test/CodeGen/X86/combine-testpd.ll b/llvm/test/CodeGen/X86/combine-testpd.ll
@@ -1,6 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
 
+;
+; testz(~X,-1) -> testc(X,-1)
+;
+
 define i32 @testpdz_128_invert(<2 x double> %c, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpdz_128_invert:
 ; CHECK:       # %bb.0:
@@ -39,6 +43,10 @@ define i32 @testpdz_256_invert(<4 x double> %c, i32 %a, i32 %b) {
   ret i32 %t5
 }
 
+;
+; testc(~X,-1) -> testz(X,-1)
+;
+
 define i32 @testpdc_128_invert(<2 x double> %c, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpdc_128_invert:
 ; CHECK:       # %bb.0:
@@ -77,6 +85,10 @@ define i32 @testpdc_256_invert(<4 x double> %c, i32 %a, i32 %b) {
   ret i32 %t5
 }
 
+;
+; testnzc(~X,-1) -> testnzc(X,-1)
+;
+
 define i32 @testpdnzc_128_invert(<2 x double> %c, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpdnzc_128_invert:
 ; CHECK:       # %bb.0:
@@ -115,6 +127,48 @@ define i32 @testpdnzc_256_invert(<4 x double> %c, i32 %a, i32 %b) {
   ret i32 %t5
 }
 
+;
+; testnzc(~X,Y) -> testnzc(X,Y)
+;
+
+define i32 @testpdnzc_128_flip(<2 x double> %c, <2 x double> %d, i32 %a, i32 %b) {
+; CHECK-LABEL: testpdnzc_128_flip:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vpxor %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vtestpd %xmm1, %xmm0
+; CHECK-NEXT:    cmovbel %esi, %eax
+; CHECK-NEXT:    retq
+  %t0 = bitcast <2 x double> %c to <2 x i64>
+  %t1 = xor <2 x i64> %t0, <i64 -1, i64 -1>
+  %t2 = bitcast <2 x i64> %t1 to <2 x double>
+  %t3 = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %t2, <2 x double> %d)
+  %t4 = icmp ne i32 %t3, 0
+  %t5 = select i1 %t4, i32 %a, i32 %b
+  ret i32 %t5
+}
+
+define i32 @testpdnzc_256_flip(<4 x double> %c, <4 x double> %d, i32 %a, i32 %b) {
+; CHECK-LABEL: testpdnzc_256_flip:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vcmptrueps %ymm2, %ymm2, %ymm2
+; CHECK-NEXT:    vxorps %ymm2, %ymm0, %ymm0
+; CHECK-NEXT:    vtestpd %ymm1, %ymm0
+; CHECK-NEXT:    cmovbel %esi, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+  %t0 = bitcast <4 x double> %c to <4 x i64>
+  %t1 = xor <4 x i64> %t0, <i64 -1, i64 -1, i64 -1, i64 -1>
+  %t2 = bitcast <4 x i64> %t1 to <4 x double>
+  %t3 = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %t2, <4 x double> %d)
+  %t4 = icmp ne i32 %t3, 0
+  %t5 = select i1 %t4, i32 %a, i32 %b
+  ret i32 %t5
+}
+
 declare i32 @llvm.x86.avx.vtestz.pd(<2 x double>, <2 x double>) nounwind readnone
 declare i32 @llvm.x86.avx.vtestc.pd(<2 x double>, <2 x double>) nounwind readnone
 declare i32 @llvm.x86.avx.vtestnzc.pd(<2 x double>, <2 x double>) nounwind readnone

diff --git a/llvm/test/CodeGen/X86/combine-testps.ll b/llvm/test/CodeGen/X86/combine-testps.ll
@@ -1,6 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
 
+;
+; testz(~X,-1) -> testc(X,-1)
+;
+
 define i32 @testpsz_128_invert(<4 x float> %c, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpsz_128_invert:
 ; CHECK:       # %bb.0:
@@ -39,6 +43,10 @@ define i32 @testpsz_256_invert(<8 x float> %c, i32 %a, i32 %b) {
   ret i32 %t5
 }
 
+;
+; testc(~X,-1) -> testz(X,-1)
+;
+
 define i32 @testpsc_128_invert(<4 x float> %c, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpsc_128_invert:
 ; CHECK:       # %bb.0:
@@ -77,6 +85,10 @@ define i32 @testpsc_256_invert(<8 x float> %c, i32 %a, i32 %b) {
   ret i32 %t5
 }
 
+;
+; testnzc(~X,-1) -> testnzc(X,-1)
+;
+
 define i32 @testpsnzc_128_invert(<4 x float> %c, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpsnzc_128_invert:
 ; CHECK:       # %bb.0:
@@ -115,6 +127,48 @@ define i32 @testpsnzc_256_invert(<8 x float> %c, i32 %a, i32 %b) {
   ret i32 %t5
 }
 
+;
+; testnzc(~X,Y) -> testnzc(X,Y)
+;
+
+define i32 @testpsnzc_128_flip(<4 x float> %c, <4 x float> %d, i32 %a, i32 %b) {
+; CHECK-LABEL: testpsnzc_128_flip:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vpxor %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vtestps %xmm1, %xmm0
+; CHECK-NEXT:    cmovbel %esi, %eax
+; CHECK-NEXT:    retq
+  %t0 = bitcast <4 x float> %c to <2 x i64>
+  %t1 = xor <2 x i64> %t0, <i64 -1, i64 -1>
+  %t2 = bitcast <2 x i64> %t1 to <4 x float>
+  %t3 = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> %t2, <4 x float> %d)
+  %t4 = icmp ne i32 %t3, 0
+  %t5 = select i1 %t4, i32 %a, i32 %b
+  ret i32 %t5
+}
+
+define i32 @testpsnzc_256_flip(<8 x float> %c, <8 x float> %d, i32 %a, i32 %b) {
+; CHECK-LABEL: testpsnzc_256_flip:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vcmptrueps %ymm2, %ymm2, %ymm2
+; CHECK-NEXT:    vxorps %ymm2, %ymm0, %ymm0
+; CHECK-NEXT:    vtestps %ymm1, %ymm0
+; CHECK-NEXT:    cmovbel %esi, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+  %t0 = bitcast <8 x float> %c to <4 x i64>
+  %t1 = xor <4 x i64> %t0, <i64 -1, i64 -1, i64 -1, i64 -1>
+  %t2 = bitcast <4 x i64> %t1 to <8 x float>
+  %t3 = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %t2, <8 x float> %d)
+  %t4 = icmp ne i32 %t3, 0
+  %t5 = select i1 %t4, i32 %a, i32 %b
+  ret i32 %t5
+}
+
 declare i32 @llvm.x86.avx.vtestz.ps(<4 x float>, <4 x float>) nounwind readnone
 declare i32 @llvm.x86.avx.vtestc.ps(<4 x float>, <4 x float>) nounwind readnone
 declare i32 @llvm.x86.avx.vtestnzc.ps(<4 x float>, <4 x float>) nounwind readnone