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ARM64: use hex immediates for movz/movk instructions
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Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to
piece together an immediate in 16-bit chunks, hex is probably the most
appropriate format.

llvm-svn: 207635
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@TNorthover
TNorthover committed Apr 30, 2014
1 parent 4b2f8a9 commit 970c4a8
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Showing 20 changed files with 150 additions and 149 deletions.
1 change: 1 addition & 0 deletions llvm/lib/Target/ARM64/ARM64InstrFormats.td
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Expand Up @@ -1275,6 +1275,7 @@ class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
def movimm32_imm : Operand<i32> {
let ParserMatchClass = Imm0_65535Operand;
let EncoderMethod = "getMoveWideImmOpValue";
let PrintMethod = "printHexImm";
}
def movimm32_shift : Operand<i32> {
let PrintMethod = "printShifter";
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10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AArch64/cond-sel.ll
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Expand Up @@ -12,8 +12,8 @@ define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
%tst1 = icmp ugt i32 %lhs32, %rhs32
%val1 = select i1 %tst1, i32 42, i32 52
store i32 %val1, i32* @var32
; CHECK-DAG: movz [[W52:w[0-9]+]], #52
; CHECK-DAG: movz [[W42:w[0-9]+]], #42
; CHECK-DAG: movz [[W52:w[0-9]+]], #{{52|0x34}}
; CHECK-DAG: movz [[W42:w[0-9]+]], #{{42|0x2a}}
; CHECK: csel {{w[0-9]+}}, [[W42]], [[W52]], hi

%rhs64 = sext i32 %rhs32 to i64
Expand All @@ -36,8 +36,8 @@ define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %r
; CHECK-NOFP-NOT: fcmp
%val1 = select i1 %tst1, i32 42, i32 52
store i32 %val1, i32* @var32
; CHECK: movz [[W52:w[0-9]+]], #52
; CHECK: movz [[W42:w[0-9]+]], #42
; CHECK: movz [[W52:w[0-9]+]], #{{52|0x34}}
; CHECK: movz [[W42:w[0-9]+]], #{{42|0x2a}}
; CHECK: csel [[MAYBETRUE:w[0-9]+]], [[W42]], [[W52]], mi
; CHECK: csel {{w[0-9]+}}, [[W42]], [[MAYBETRUE]], gt

Expand All @@ -49,7 +49,7 @@ define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %r
store i64 %val2, i64* @var64
; CHECK-AARCH64: movz x[[CONST15:[0-9]+]], #15
; CHECK-ARM64: orr w[[CONST15:[0-9]+]], wzr, #0xf
; CHECK: movz {{[wx]}}[[CONST9:[0-9]+]], #9
; CHECK: movz {{[wx]}}[[CONST9:[0-9]+]], #{{9|0x9}}
; CHECK: csel [[MAYBETRUE:x[0-9]+]], x[[CONST9]], x[[CONST15]], eq
; CHECK: csel {{x[0-9]+}}, x[[CONST9]], [[MAYBETRUE]], vs

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/func-calls.ll
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Expand Up @@ -114,10 +114,10 @@ define void @check_stack_args() {
; CHECK-AARCH64: mov x0, sp
; CHECK-AARCH64: str d[[STACKEDREG]], [x0]

; CHECK-ARM64: movz [[SIXTY_FOUR:w[0-9]+]], #17024, lsl #16
; CHECK-ARM64: movz [[SIXTY_FOUR:w[0-9]+]], #0x4280, lsl #16
; CHECK-ARM64: str [[SIXTY_FOUR]], [sp]

; CHECK-ARM64-NONEON: movz [[SIXTY_FOUR:w[0-9]+]], #17024, lsl #16
; CHECK-ARM64-NONEON: movz [[SIXTY_FOUR:w[0-9]+]], #0x4280, lsl #16
; CHECK-ARM64-NONEON: str [[SIXTY_FOUR]], [sp]

; CHECK: bl stacked_fpu
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/movw-consts.ll
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Expand Up @@ -61,7 +61,7 @@ define i64 @test7() {
; couldn't. Useful even for i64
define i64 @test8() {
; CHECK-LABEL: test8:
; CHECK: movn w0, #60875
; CHECK: movn w0, #{{60875|0xedcb}}
ret i64 4294906420
}

Expand All @@ -73,7 +73,7 @@ define i64 @test9() {

define i64 @test10() {
; CHECK-LABEL: test10:
; CHECK: movn x0, #60875, lsl #16
; CHECK: movn x0, #{{60875|0xedcb}}, lsl #16
ret i64 18446744069720047615
}

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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/ARM64/abi_align.ll
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Expand Up @@ -74,7 +74,7 @@ define i32 @caller38_stack() #1 {
entry:
; CHECK: caller38_stack
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8]
; CHECK: movz w[[C:[0-9]+]], #9
; CHECK: movz w[[C:[0-9]+]], #0x9
; CHECK: str w[[C]], [sp]
%0 = load i64* bitcast (%struct.s38* @g38 to i64*), align 4
%1 = load i64* bitcast (%struct.s38* @g38_2 to i64*), align 4
Expand Down Expand Up @@ -128,7 +128,7 @@ entry:
; CHECK: caller39_stack
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #32]
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
; CHECK: movz w[[C:[0-9]+]], #9
; CHECK: movz w[[C:[0-9]+]], #0x9
; CHECK: str w[[C]], [sp]
%0 = load i128* bitcast (%struct.s39* @g39 to i128*), align 16
%1 = load i128* bitcast (%struct.s39* @g39_2 to i128*), align 16
Expand Down Expand Up @@ -184,7 +184,7 @@ entry:
; CHECK: caller40_stack
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #24]
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8]
; CHECK: movz w[[C:[0-9]+]], #9
; CHECK: movz w[[C:[0-9]+]], #0x9
; CHECK: str w[[C]], [sp]
%0 = load [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4
%1 = load [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4
Expand Down Expand Up @@ -238,7 +238,7 @@ entry:
; CHECK: caller41_stack
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #32]
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
; CHECK: movz w[[C:[0-9]+]], #9
; CHECK: movz w[[C:[0-9]+]], #0x9
; CHECK: str w[[C]], [sp]
%0 = load i128* bitcast (%struct.s41* @g41 to i128*), align 16
%1 = load i128* bitcast (%struct.s41* @g41_2 to i128*), align 16
Expand Down Expand Up @@ -330,7 +330,7 @@ entry:
; CHECK: sub x[[A:[0-9]+]], x29, #32
; Address of s1 is passed on stack at sp+8
; CHECK: str x[[A]], [sp, #8]
; CHECK: movz w[[C:[0-9]+]], #9
; CHECK: movz w[[C:[0-9]+]], #0x9
; CHECK: str w[[C]], [sp]

; FAST: caller42_stack
Expand Down Expand Up @@ -442,7 +442,7 @@ entry:
; CHECK: sub x[[A:[0-9]+]], x29, #32
; Address of s1 is passed on stack at sp+8
; CHECK: str x[[A]], [sp, #8]
; CHECK: movz w[[C:[0-9]+]], #9
; CHECK: movz w[[C:[0-9]+]], #0x9
; CHECK: str w[[C]], [sp]

; FAST: caller43_stack
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM64/atomic.ll
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Expand Up @@ -57,7 +57,7 @@ define i64 @fetch_and_nand_64(i64* %p) {

define i32 @fetch_and_or(i32* %p) {
; CHECK-LABEL: fetch_and_or:
; CHECK: movz [[OLDVAL_REG:w[0-9]+]], #5
; CHECK: movz [[OLDVAL_REG:w[0-9]+]], #0x5
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0]
; CHECK: orr [[SCRATCH2_REG:w[0-9]+]], w[[DEST_REG]], [[OLDVAL_REG]]
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/ARM64/bitfield-extract.ll
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Expand Up @@ -348,8 +348,8 @@ entry:
; CHECK-LABEL: fct16:
; CHECK: ldr [[REG1:w[0-9]+]],
; Create the constant
; CHECK: movz [[REGCST:w[0-9]+]], #26, lsl #16
; CHECK: movk [[REGCST]], #33120
; CHECK: movz [[REGCST:w[0-9]+]], #0x1a, lsl #16
; CHECK: movk [[REGCST]], #0x8160
; Do the masking
; CHECK: and [[REG2:w[0-9]+]], [[REG1]], [[REGCST]]
; CHECK-NEXT: bfm [[REG2]], w1, #16, #18
Expand Down Expand Up @@ -377,8 +377,8 @@ entry:
; CHECK-LABEL: fct17:
; CHECK: ldr [[REG1:x[0-9]+]],
; Create the constant
; CHECK: movz w[[REGCST:[0-9]+]], #26, lsl #16
; CHECK: movk w[[REGCST]], #33120
; CHECK: movz w[[REGCST:[0-9]+]], #0x1a, lsl #16
; CHECK: movk w[[REGCST]], #0x8160
; Do the masking
; CHECK: and [[REG2:x[0-9]+]], [[REG1]], x[[REGCST]]
; CHECK-NEXT: bfm [[REG2]], x1, #16, #18
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM64/const-addr.ll
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Expand Up @@ -5,8 +5,8 @@
; Test if the constant base address gets only materialized once.
define i32 @test1() nounwind {
; CHECK-LABEL: test1
; CHECK: movz w8, #1039, lsl #16
; CHECK-NEXT: movk w8, #49152
; CHECK: movz w8, #0x40f, lsl #16
; CHECK-NEXT: movk w8, #0xc000
; CHECK-NEXT: ldp w9, w10, [x8, #4]
; CHECK: ldr w8, [x8, #12]
%at = inttoptr i64 68141056 to %T*
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10 changes: 5 additions & 5 deletions llvm/test/CodeGen/ARM64/fast-isel-addr-offset.ll
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Expand Up @@ -9,7 +9,7 @@ entry:
; CHECK: @foo
; CHECK: adrp x[[REG:[0-9]+]], _sortlist@GOTPAGE
; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _sortlist@GOTPAGEOFF]
; CHECK: movz x[[REG2:[0-9]+]], #20000
; CHECK: movz x[[REG2:[0-9]+]], #0x4e20
; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]]
; CHECK: ldr w0, [x[[REG3]]]
; CHECK: ret
Expand All @@ -22,7 +22,7 @@ entry:
; CHECK: @foo2
; CHECK: adrp x[[REG:[0-9]+]], _sortlist2@GOTPAGE
; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _sortlist2@GOTPAGEOFF]
; CHECK: movz x[[REG2:[0-9]+]], #40000
; CHECK: movz x[[REG2:[0-9]+]], #0x9c40
; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]]
; CHECK: ldr x0, [x[[REG3]]]
; CHECK: ret
Expand All @@ -37,9 +37,9 @@ entry:
define signext i8 @foo3() nounwind ssp {
entry:
; CHECK: @foo3
; CHECK: movz x[[REG:[0-9]+]], #2874, lsl #32
; CHECK: movk x[[REG]], #29646, lsl #16
; CHECK: movk x[[REG]], #12274
; CHECK: movz x[[REG:[0-9]+]], #0xb3a, lsl #32
; CHECK: movk x[[REG]], #0x73ce, lsl #16
; CHECK: movk x[[REG]], #0x2ff2
%0 = load i8** @pd2, align 8
%arrayidx = getelementptr inbounds i8* %0, i64 12345678901234
%1 = load i8* %arrayidx, align 1
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM64/fast-isel-gv.ll
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Expand Up @@ -18,10 +18,10 @@ entry:
; CHECK: @Rand
; CHECK: adrp x[[REG:[0-9]+]], _seed@GOTPAGE
; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]], _seed@GOTPAGEOFF]
; CHECK: movz x[[REG3:[0-9]+]], #1309
; CHECK: movz x[[REG3:[0-9]+]], #0x51d
; CHECK: ldr x[[REG4:[0-9]+]], [x[[REG2]]]
; CHECK: mul x[[REG5:[0-9]+]], x[[REG4]], x[[REG3]]
; CHECK: movz x[[REG6:[0-9]+]], #13849
; CHECK: movz x[[REG6:[0-9]+]], #0x3619
; CHECK: add x[[REG7:[0-9]+]], x[[REG5]], x[[REG6]]
; CHECK: orr x[[REG8:[0-9]+]], xzr, #0xffff
; CHECK: and x[[REG9:[0-9]+]], x[[REG7]], x[[REG8]]
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/ARM64/fast-isel-intrinsic.ll
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Expand Up @@ -4,11 +4,11 @@
@temp = common global [80 x i8] zeroinitializer, align 16

define void @t1() {
; ARM64: t1
; ARM64-LABEL: t1
; ARM64: adrp x8, _message@PAGE
; ARM64: add x0, x8, _message@PAGEOFF
; ARM64: movz w9, #0
; ARM64: movz x2, #80
; ARM64: movz x2, #0x50
; ARM64: uxtb w1, w9
; ARM64: bl _memset
call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i8 0, i64 80, i32 16, i1 false)
Expand All @@ -18,12 +18,12 @@ define void @t1() {
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)

define void @t2() {
; ARM64: t2
; ARM64-LABEL: t2
; ARM64: adrp x8, _temp@GOTPAGE
; ARM64: ldr x0, [x8, _temp@GOTPAGEOFF]
; ARM64: adrp x8, _message@PAGE
; ARM64: add x1, x8, _message@PAGEOFF
; ARM64: movz x2, #80
; ARM64: movz x2, #0x50
; ARM64: bl _memcpy
call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 80, i32 16, i1 false)
ret void
Expand All @@ -32,12 +32,12 @@ define void @t2() {
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1)

define void @t3() {
; ARM64: t3
; ARM64-LABEL: t3
; ARM64: adrp x8, _temp@GOTPAGE
; ARM64: ldr x0, [x8, _temp@GOTPAGEOFF]
; ARM64: adrp x8, _message@PAGE
; ARM64: add x1, x8, _message@PAGEOFF
; ARM64: movz x2, #20
; ARM64: movz x2, #0x14
; ARM64: bl _memmove
call void @llvm.memmove.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 20, i32 16, i1 false)
ret void
Expand All @@ -46,7 +46,7 @@ define void @t3() {
declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1)

define void @t4() {
; ARM64: t4
; ARM64-LABEL: t4
; ARM64: adrp x8, _temp@GOTPAGE
; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF]
; ARM64: adrp x9, _message@PAGE
Expand All @@ -63,7 +63,7 @@ define void @t4() {
}

define void @t5() {
; ARM64: t5
; ARM64-LABEL: t5
; ARM64: adrp x8, _temp@GOTPAGE
; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF]
; ARM64: adrp x9, _message@PAGE
Expand All @@ -80,7 +80,7 @@ define void @t5() {
}

define void @t6() {
; ARM64: t6
; ARM64-LABEL: t6
; ARM64: adrp x8, _temp@GOTPAGE
; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF]
; ARM64: adrp x9, _message@PAGE
Expand All @@ -97,7 +97,7 @@ define void @t6() {
}

define void @t7() {
; ARM64: t7
; ARM64-LABEL: t7
; ARM64: adrp x8, _temp@GOTPAGE
; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF]
; ARM64: adrp x9, _message@PAGE
Expand All @@ -116,7 +116,7 @@ define void @t7() {
}

define void @t8() {
; ARM64: t8
; ARM64-LABEL: t8
; ARM64: adrp x8, _temp@GOTPAGE
; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF]
; ARM64: adrp x9, _message@PAGE
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM64/fp128.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -186,13 +186,13 @@ define i32 @test_br_cc() {
iftrue:
ret i32 42
; CHECK-NEXT: BB#
; CHECK-NEXT: movz w0, #42
; CHECK-NEXT: movz w0, #0x2a
; CHECK-NEXT: b [[REALRET:.LBB[0-9]+_[0-9]+]]

iffalse:
ret i32 29
; CHECK: [[RET29]]:
; CHECK-NEXT: movz w0, #29
; CHECK-NEXT: movz w0, #0x1d
; CHECK-NEXT: [[REALRET]]:
; CHECK: ret
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM64/memcpy-inline.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,7 @@ define void @t5(i8* nocapture %C) nounwind {
entry:
; CHECK-LABEL: t5:
; CHECK: strb wzr, [x0, #6]
; CHECK: movz [[REG7:w[0-9]+]], #21587
; CHECK: movz [[REG7:w[0-9]+]], #0x5453
; CHECK: strh [[REG7]], [x0, #4]
; CHECK: movz [[REG8:w[0-9]+]],
; CHECK: movk [[REG8]],
Expand Down
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