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llvm-tblgen: Rewrite emitters to use TableGen::Emitter
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Each emitter became self-contained since it has the registration of option.

Differential Revision: https://reviews.llvm.org/D144351
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chapuni committed Mar 21, 2023
1 parent a7e2b74 commit 9c93e72
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Showing 33 changed files with 133 additions and 486 deletions.
11 changes: 2 additions & 9 deletions llvm/utils/TableGen/AsmMatcherEmitter.cpp
Expand Up @@ -100,15 +100,13 @@
#include "CodeGenRegisters.h"
#include "CodeGenTarget.h"
#include "SubtargetFeatureInfo.h"
#include "TableGenBackends.h"
#include "Types.h"
#include "llvm/ADT/CachedHashString.h"
#include "llvm/ADT/PointerUnion.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/Config/llvm-config.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
Expand Down Expand Up @@ -4004,10 +4002,5 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
OS << "#endif // GET_MNEMONIC_CHECKER\n\n";
}

namespace llvm {

void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
AsmMatcherEmitter(RK).run(OS);
}

} // end namespace llvm
static TableGen::Emitter::OptClass<AsmMatcherEmitter>
X("gen-asm-matcher", "Generate assembly instruction matcher");
10 changes: 2 additions & 8 deletions llvm/utils/TableGen/AsmWriterEmitter.cpp
Expand Up @@ -17,7 +17,6 @@
#include "CodeGenRegisters.h"
#include "CodeGenTarget.h"
#include "SequenceToOffsetTable.h"
#include "TableGenBackends.h"
#include "Types.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
Expand Down Expand Up @@ -1310,10 +1309,5 @@ void AsmWriterEmitter::run(raw_ostream &O) {
EmitPrintAliasInstruction(O);
}

namespace llvm {

void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) {
AsmWriterEmitter(RK).run(OS);
}

} // end namespace llvm
static TableGen::Emitter::OptClass<AsmWriterEmitter>
X("gen-asm-writer", "Generate assembly writer");
11 changes: 3 additions & 8 deletions llvm/utils/TableGen/Attributes.cpp
Expand Up @@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//

#include "TableGenBackends.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
#include <vector>
using namespace llvm;

Expand Down Expand Up @@ -130,10 +130,5 @@ void Attributes::run(raw_ostream &OS) {
emitAttributeProperties(OS);
}

namespace llvm {

void EmitAttributes(RecordKeeper &RK, raw_ostream &OS) {
Attributes(RK).run(OS);
}

} // namespace llvm
static TableGen::Emitter::OptClass<Attributes> X("gen-attrs",
"Generate attributes");
9 changes: 3 additions & 6 deletions llvm/utils/TableGen/CTagsEmitter.cpp
Expand Up @@ -12,11 +12,11 @@
//
//===----------------------------------------------------------------------===//

#include "TableGenBackends.h"
#include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
#include <algorithm>
#include <vector>
using namespace llvm;
Expand Down Expand Up @@ -86,8 +86,5 @@ void CTagsEmitter::run(raw_ostream &OS) {
T.emit(OS);
}

namespace llvm {

void EmitCTags(RecordKeeper &RK, raw_ostream &OS) { CTagsEmitter(RK).run(OS); }

} // namespace llvm
static TableGen::Emitter::OptClass<CTagsEmitter>
X("gen-ctags", "Generate ctags-compatible index");
10 changes: 2 additions & 8 deletions llvm/utils/TableGen/CallingConvEmitter.cpp
Expand Up @@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===//

#include "CodeGenTarget.h"
#include "TableGenBackends.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
Expand Down Expand Up @@ -429,10 +428,5 @@ void CallingConvEmitter::EmitArgRegisterLists(raw_ostream &O) {
}
}

namespace llvm {

void EmitCallingConv(RecordKeeper &RK, raw_ostream &OS) {
CallingConvEmitter(RK).run(OS);
}

} // namespace llvm
static TableGen::Emitter::OptClass<CallingConvEmitter>
X("gen-callingconv", "Generate calling convention descriptions");
10 changes: 2 additions & 8 deletions llvm/utils/TableGen/CodeEmitterGen.cpp
Expand Up @@ -16,7 +16,6 @@
#include "CodeGenInstruction.h"
#include "CodeGenTarget.h"
#include "InfoByHwMode.h"
#include "TableGenBackends.h"
#include "VarLenCodeEmitterGen.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
Expand Down Expand Up @@ -504,10 +503,5 @@ void CodeEmitterGen::run(raw_ostream &o) {

} // end anonymous namespace

namespace llvm {

void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) {
CodeEmitterGen(RK).run(OS);
}

} // end namespace llvm
static TableGen::Emitter::OptClass<CodeEmitterGen>
X("gen-emitter", "Generate machine code emitter");
10 changes: 2 additions & 8 deletions llvm/utils/TableGen/CompressInstEmitter.cpp
Expand Up @@ -67,7 +67,6 @@
#include "CodeGenInstruction.h"
#include "CodeGenRegisters.h"
#include "CodeGenTarget.h"
#include "TableGenBackends.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringMap.h"
Expand Down Expand Up @@ -904,10 +903,5 @@ void CompressInstEmitter::run(raw_ostream &o) {
emitCompressInstEmitter(o, EmitterType::CheckCompress);
}

namespace llvm {

void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS) {
CompressInstEmitter(RK).run(OS);
}

} // namespace llvm
static TableGen::Emitter::OptClass<CompressInstEmitter>
X("gen-compress-inst-emitter", "Generate RISCV compressed instructions.");
10 changes: 2 additions & 8 deletions llvm/utils/TableGen/DAGISelEmitter.cpp
Expand Up @@ -14,7 +14,6 @@
#include "CodeGenInstruction.h"
#include "CodeGenTarget.h"
#include "DAGISelMatcher.h"
#include "TableGenBackends.h"
#include "llvm/Support/Debug.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
Expand Down Expand Up @@ -188,10 +187,5 @@ void DAGISelEmitter::run(raw_ostream &OS) {
EmitMatcherTable(TheMatcher.get(), CGP, OS);
}

namespace llvm {

void EmitDAGISel(RecordKeeper &RK, raw_ostream &OS) {
DAGISelEmitter(RK).run(OS);
}

} // namespace llvm
static TableGen::Emitter::OptClass<DAGISelEmitter>
X("gen-dag-isel", "Generate a DAG instruction selector");
11 changes: 3 additions & 8 deletions llvm/utils/TableGen/DFAEmitter.cpp
Expand Up @@ -22,13 +22,13 @@

#include "DFAEmitter.h"
#include "SequenceToOffsetTable.h"
#include "TableGenBackends.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/UniqueVector.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
#include <cassert>
#include <cstdint>
#include <deque>
Expand Down Expand Up @@ -370,10 +370,5 @@ void CustomDfaEmitter::printActionValue(action_type A, raw_ostream &OS) {
OS << ")";
}

namespace llvm {

void EmitAutomata(RecordKeeper &RK, raw_ostream &OS) {
AutomatonEmitter(RK).run(OS);
}

} // namespace llvm
static TableGen::Emitter::OptClass<AutomatonEmitter>
X("gen-automata", "Generate generic automata");
10 changes: 2 additions & 8 deletions llvm/utils/TableGen/DFAPacketizerEmitter.cpp
Expand Up @@ -17,7 +17,6 @@
#include "CodeGenSchedule.h"
#include "CodeGenTarget.h"
#include "DFAEmitter.h"
#include "TableGenBackends.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
Expand Down Expand Up @@ -354,10 +353,5 @@ void DFAPacketizerEmitter::emitForItineraries(
<< "\n}\n\n";
}

namespace llvm {

void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) {
DFAPacketizerEmitter(RK).run(OS);
}

} // end namespace llvm
static TableGen::Emitter::OptClass<DFAPacketizerEmitter>
X("gen-dfa-packetizer", "Generate DFA Packetizer for VLIW targets");
9 changes: 4 additions & 5 deletions llvm/utils/TableGen/DXILEmitter.cpp
Expand Up @@ -12,13 +12,13 @@
//===----------------------------------------------------------------------===//

#include "SequenceToOffsetTable.h"
#include "TableGenBackends.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/Support/DXILOperationCommon.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"

using namespace llvm;
using namespace llvm::dxil;
Expand Down Expand Up @@ -411,9 +411,7 @@ static void emitDXILOperationTable(std::vector<DXILOperationData> &DXILOps,
OS << "}\n ";
}

namespace llvm {

void EmitDXILOperation(RecordKeeper &Records, raw_ostream &OS) {
static void EmitDXILOperation(RecordKeeper &Records, raw_ostream &OS) {
std::vector<Record *> Ops = Records.getAllDerivedDefinitions("dxil_op");
OS << "// Generated code, do not edit.\n";
OS << "\n";
Expand All @@ -439,4 +437,5 @@ void EmitDXILOperation(RecordKeeper &Records, raw_ostream &OS) {
OS << "\n";
}

} // namespace llvm
static TableGen::Emitter::Opt X("gen-dxil-operation", EmitDXILOperation,
"Generate DXIL operation information");
20 changes: 10 additions & 10 deletions llvm/utils/TableGen/DirectiveEmitter.cpp
Expand Up @@ -12,13 +12,13 @@
//===----------------------------------------------------------------------===//

#include "llvm/TableGen/DirectiveEmitter.h"
#include "TableGenBackends.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"

using namespace llvm;

Expand Down Expand Up @@ -174,11 +174,9 @@ bool DirectiveLanguage::HasValidityErrors() const {
return HasDuplicateClausesInDirectives(getDirectives());
}

namespace llvm {

// Generate the declaration section for the enumeration in the directive
// language
void EmitDirectivesDecl(RecordKeeper &Records, raw_ostream &OS) {
static void EmitDirectivesDecl(RecordKeeper &Records, raw_ostream &OS) {
const auto DirLang = DirectiveLanguage{Records};
if (DirLang.HasValidityErrors())
return;
Expand Down Expand Up @@ -247,8 +245,6 @@ void EmitDirectivesDecl(RecordKeeper &Records, raw_ostream &OS) {
OS << "#endif // LLVM_" << DirLang.getName() << "_INC\n";
}

} // namespace llvm

// Generate function implementation for get<Enum>Name(StringRef Str)
static void GenerateGetName(const std::vector<Record *> &Records,
raw_ostream &OS, StringRef Enum,
Expand Down Expand Up @@ -877,11 +873,9 @@ void EmitDirectivesBasicImpl(const DirectiveLanguage &DirLang,
GenerateIsAllowedClause(DirLang, OS);
}

namespace llvm {

// Generate the implemenation section for the enumeration in the directive
// language.
void EmitDirectivesImpl(RecordKeeper &Records, raw_ostream &OS) {
static void EmitDirectivesImpl(RecordKeeper &Records, raw_ostream &OS) {
const auto DirLang = DirectiveLanguage{Records};
if (DirLang.HasValidityErrors())
return;
Expand All @@ -893,4 +887,10 @@ void EmitDirectivesImpl(RecordKeeper &Records, raw_ostream &OS) {
EmitDirectivesBasicImpl(DirLang, OS);
}

} // namespace llvm
static TableGen::Emitter::Opt
X("gen-directive-decl", EmitDirectivesDecl,
"Generate directive related declaration code (header file)");

static TableGen::Emitter::Opt
Y("gen-directive-impl", EmitDirectivesImpl,
"Generate directive related implementation code");
7 changes: 3 additions & 4 deletions llvm/utils/TableGen/DisassemblerEmitter.cpp
Expand Up @@ -94,9 +94,7 @@ using namespace llvm::X86Disassembler;
/// X86RecognizableInstr.cpp contains the implementation for a single
/// instruction.

namespace llvm {

void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) {
static void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) {
CodeGenTarget Target(Records);
emitSourceFileHeader(" * " + Target.getName().str() + " Disassembler", OS);

Expand Down Expand Up @@ -133,4 +131,5 @@ void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) {
EmitDecoder(Records, OS, PredicateNamespace);
}

} // end namespace llvm
static TableGen::Emitter::Opt X("gen-disassembler", EmitDisassembler,
"Generate disassembler");
10 changes: 2 additions & 8 deletions llvm/utils/TableGen/ExegesisEmitter.cpp
Expand Up @@ -10,7 +10,6 @@
//
//===----------------------------------------------------------------------===//

#include "TableGenBackends.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringRef.h"
Expand Down Expand Up @@ -203,10 +202,5 @@ void ExegesisEmitter::run(raw_ostream &OS) const {

} // end anonymous namespace

namespace llvm {

void EmitExegesis(RecordKeeper &RK, raw_ostream &OS) {
ExegesisEmitter(RK).run(OS);
}

} // end namespace llvm
static TableGen::Emitter::OptClass<ExegesisEmitter>
X("gen-exegesis", "Generate llvm-exegesis tables");
8 changes: 3 additions & 5 deletions llvm/utils/TableGen/FastISelEmitter.cpp
Expand Up @@ -21,7 +21,6 @@
#include "CodeGenRegisters.h"
#include "CodeGenTarget.h"
#include "InfoByHwMode.h"
#include "TableGenBackends.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/TableGen/Error.h"
Expand Down Expand Up @@ -858,9 +857,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
// TODO: SignaturesWithConstantForms should be empty here.
}

namespace llvm {

void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
static void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
CodeGenDAGPatterns CGP(RK);
const CodeGenTarget &Target = CGP.getTargetInfo();
emitSourceFileHeader("\"Fast\" Instruction Selector for the " +
Expand All @@ -876,4 +873,5 @@ void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
F.printFunctionDefinitions(OS);
}

} // namespace llvm
static TableGen::Emitter::Opt X("gen-fast-isel", EmitFastISel,
"Generate a \"fast\" instruction selector");

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