[flang][clang][docs] Split out Clang specific doc text for -mrvv-vect…

…or-bits

Flang does not set the preprocessor define.

clang/include/clang/Driver/Options.td

@@ -4660,11 +4660,15 @@ def menable_experimental_extensions : Flag<["-"], "menable-experimental-extensio
 def mrvv_vector_bits_EQ : Joined<["-"], "mrvv-vector-bits=">, Group<m_Group>,
   Visibility<[ClangOption, FlangOption]>,
   HelpText<"Specify the size in bits of an RVV vector register">,
-  DocBrief<"Defaults to the vector length agnostic value of \"scalable\". "
-           "Accepts power of 2 values between 64 and 65536. Also accepts "
-           "\"zvl\" to use the value implied by -march/-mcpu. On Clang, value "
-           "will be reflected in __riscv_v_fixed_vlen preprocessor define "
-           "(RISC-V only)">;
+  DocBrief<!strconcat(
+    "Defaults to the vector length agnostic value of \"scalable\". "
+    "Accepts power of 2 values between 64 and 65536. Also accepts "
+    "\"zvl\" to use the value implied by -march/-mcpu.",
+    !cond(
+      // Flang does not set the preprocessor define.
+      !eq(GlobalDocumentation.Program, "Flang") : "",
+      true: " The value will be reflected in __riscv_v_fixed_vlen preprocessor define"),
+    " (RISC-V only)")>;
 
 def munaligned_access : Flag<["-"], "munaligned-access">, Group<m_Group>,
   HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64/LoongArch/RISC-V only)">;