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Revert "[ARM] Adjust strd/ldrd codegen alignment requirements"
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This reverts commit 92a9c30.

This has caused a test failure in the 2nd stage of Linaro's
Arm 32 bit buildbots.

LLVM::simplified-template-names.s

            7: error: Simplified template DW_AT_name could not be reconstituted:
check:10'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            8:  original: f3<unsigned char, (unsigned char)'\x00'>
check:10'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            9:  reconstituted: f3<unsigned char, (unsigned char)'\x7f'>
check:10'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

I suspect a load/store is slightly off.
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@DavidSpickett
DavidSpickett committed Jul 3, 2023
1 parent 29f4c39 commit ab3bb86
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Showing 18 changed files with 278 additions and 265 deletions.
5 changes: 4 additions & 1 deletion llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2289,7 +2289,10 @@ bool ARMPreAllocLoadStoreOpt::CanFormLdStDWord(
return false;

Align Alignment = (*Op0->memoperands_begin())->getAlign();
Align ReqAlign = STI->getDualLoadStoreAlignment();
const Function &Func = MF->getFunction();
Align ReqAlign =
STI->hasV6Ops() ? TD->getABITypeAlign(Type::getInt64Ty(Func.getContext()))
: Align(8); // Pre-v6 need 8-byte align
if (Alignment < ReqAlign)
return false;

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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/ARM/copy-by-struct-i32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -21,8 +21,9 @@ define arm_aapcscc void @s(ptr %q, ptr %p) {
; ASSEMBLY-NEXT: sbc r5, r5, #0
; ASSEMBLY-NEXT: ldr r2, [r1, #8]
; ASSEMBLY-NEXT: ldr r3, [r1, #12]
; ASSEMBLY-NEXT: strd r4, r5, [sp, #128]
; ASSEMBLY-NEXT: str r5, [sp, #132]
; ASSEMBLY-NEXT: add r5, r1, #16
; ASSEMBLY-NEXT: str r4, [sp, #128]
; ASSEMBLY-NEXT: mov r4, sp
; ASSEMBLY-NEXT: vld1.32 {d16}, [r5]!
; ASSEMBLY-NEXT: vst1.32 {d16}, [r4]!
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18 changes: 10 additions & 8 deletions llvm/test/CodeGen/ARM/ha-alignstack-call.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -81,10 +81,11 @@ entry:
ret float %call
}
; CHECK-LABEL: f1_1_call:
; CHECK: movw r0, #52429
; CHECK: mov r1, #0
; CHECK: movt r0, #16204
; CHECK-DAG: strd r0, r1, [sp]
; CHECK: movw r1, #52429
; CHECK: mov r0, #0
; CHECK: movt r1, #16204
; CHECK-DAG: str r1, [sp]
; CHECK-DAG: str r0, [sp, #4]
; CHECK: bl f1_1

; pass in memory, alignment 8
Expand All @@ -95,12 +96,13 @@ entry:
ret float %call
}
; CHECK-LABEL: f1_2_call:
; CHECK-DAG: movw r0, #26214
; CHECK-DAG: mov r1, #0
; CHECK: movt r0, #16230
; CHECK: strd r0, r1, [sp, #8]
; CHECK-DAG: mov r0, #0
; CHECK-DAG: movw r1, #26214
; CHECK: str r0, [sp, #12]
; CHECK: movw r0, #52429
; CHECK: movt r1, #16230
; CHECK: movt r0, #16204
; CHECK-DAG: str r1, [sp, #8]
; CHECK-DAG: str r0, [sp]
; CHECK: bl f1_2

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11 changes: 5 additions & 6 deletions llvm/test/CodeGen/ARM/indexed-mem.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -225,8 +225,7 @@ define ptr @post_inc_ldrd(ptr %base, ptr %addr.3) {
;
; CHECK-V8A-LABEL: post_inc_ldrd:
; CHECK-V8A: @ %bb.0:
; CHECK-V8A-NEXT: ldrd r2, r3, [r0]
; CHECK-V8A-NEXT: add r0, r0, #8
; CHECK-V8A-NEXT: ldm r0!, {r2, r3}
; CHECK-V8A-NEXT: add r2, r2, r3
; CHECK-V8A-NEXT: str r2, [r1]
; CHECK-V8A-NEXT: bx lr
Expand All @@ -249,8 +248,8 @@ define ptr @pre_inc_str_multi(ptr %base) {
;
; CHECK-V8A-LABEL: pre_inc_str_multi:
; CHECK-V8A: @ %bb.0:
; CHECK-V8A-NEXT: ldrd r2, r3, [r0]
; CHECK-V8A-NEXT: add r1, r2, r3
; CHECK-V8A-NEXT: ldm r0, {r1, r2}
; CHECK-V8A-NEXT: add r1, r1, r2
; CHECK-V8A-NEXT: str r1, [r0, #8]!
; CHECK-V8A-NEXT: bx lr
%addr.1 = getelementptr i32, ptr %base, i32 1
Expand All @@ -272,8 +271,8 @@ define ptr @pre_dec_str_multi(ptr %base) {
;
; CHECK-V8A-LABEL: pre_dec_str_multi:
; CHECK-V8A: @ %bb.0:
; CHECK-V8A-NEXT: ldrd r2, r3, [r0]
; CHECK-V8A-NEXT: add r1, r2, r3
; CHECK-V8A-NEXT: ldm r0, {r1, r2}
; CHECK-V8A-NEXT: add r1, r1, r2
; CHECK-V8A-NEXT: str r1, [r0, #-4]!
; CHECK-V8A-NEXT: bx lr
%addr.1 = getelementptr i32, ptr %base, i32 1
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6 changes: 4 additions & 2 deletions llvm/test/CodeGen/ARM/prera-ldst-aliasing.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -30,8 +30,10 @@ body: |
t2STRi12 killed %2, %0, 0, 14, $noreg :: (store (s32) into %ir.x)
%3 : gpr = t2LDRi12 %1, 4, 14, $noreg :: (load (s32) from %ir.arrayidx2)
t2STRi12 killed %3, %0, 4, 14, $noreg :: (store (s32) into %ir.arrayidx3)
; CHECK: t2LDRDi8
; CHECK-NEXT: t2STRDi8
; CHECK: t2LDRi12
; CHECK-NEXT: t2LDRi12
; CHECK-NEXT: t2STRi12
; CHECK-NEXT: t2STRi12
tBX_RET 14, $noreg
...
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12 changes: 8 additions & 4 deletions llvm/test/CodeGen/ARM/prera-ldst-insertpt.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,8 @@ body: |
; Make sure we move the paired stores next to each other, and
; insert them in an appropriate location.
; CHECK: t2STRDi8 %1, %10,
; CHECK: t2STRi12 %1,
; CHECK-NEXT: t2STRi12 killed %10,
; CHECK-NEXT: t2MOVi
; CHECK-NEXT: t2ADDrs
Expand All @@ -52,7 +53,8 @@ body: |
t2STRi12 killed %13, %0, 20, 14, $noreg :: (store (s32))
; Make sure we move the paired stores next to each other.
; CHECK: t2STRDi8 %12, %13,
; CHECK: t2STRi12 killed %12,
; CHECK-NEXT: t2STRi12 killed %13,
tBX_RET 14, $noreg
---
Expand Down Expand Up @@ -86,7 +88,8 @@ body: |
; CHECK-NEXT: t2MOVi32imm
; CHECK-LIMIT-LABEL: name: b
; CHECK-LIMIT: t2STRDi8 {{.*}}, {{.*}}, {{.*}}, 0
; CHECK-LIMIT: t2STRi12 {{.*}}, 0
; CHECK-LIMIT-NEXT: t2STRi12 {{.*}}, 4
; CHECK-LIMIT-NEXT: t2MUL
; CHECK-LIMIT-NEXT: t2STRi12 {{.*}}, 8
Expand All @@ -102,7 +105,8 @@ body: |
t2STRi12 killed %13, %0, 20, 14, $noreg :: (store (s32))
; Make sure we move the paired stores next to each other.
; CHECK: t2STRDi8 %12, %13, %0, 16
; CHECK: t2STRi12 {{.*}}, 16
; CHECK-NEXT: t2STRi12 {{.*}}, 20
tBX_RET 14, $noreg
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM/vector-DAGCombine.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -134,8 +134,8 @@ define void @i64_buildvector(ptr %ptr, ptr %vp) nounwind {
define void @i64_insertelement(ptr %ptr, ptr %vp) nounwind {
; CHECK-LABEL: i64_insertelement:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldm r0, {r0, r3}
; CHECK-NEXT: stm r1, {r0, r3}
; CHECK-NEXT: ldm r0, {r2, r3}
; CHECK-NEXT: strd r2, r3, [r1]
; CHECK-NEXT: bx lr
%t0 = load i64, ptr %ptr, align 4
%vec = load <2 x i64>, ptr %vp
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114 changes: 57 additions & 57 deletions llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -165,74 +165,74 @@ define dso_local i32 @b(ptr %c, i32 %d, i32 %e, ptr %n) "frame-pointer"="all" {
; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: wls lr, r1, .LBB2_3
; CHECK-NEXT: @ %bb.1: @ %while.body.preheader
; CHECK-NEXT: adds r6, r3, #4
; CHECK-NEXT: adds r1, r0, #4
; CHECK-NEXT: mvn r8, #1
; CHECK-NEXT: @ implicit-def: $r9
; CHECK-NEXT: mov r12, r0
; CHECK-NEXT: add.w r10, r3, #4
; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: mvn r9, #1
; CHECK-NEXT: @ implicit-def: $r8
; CHECK-NEXT: @ implicit-def: $r4
; CHECK-NEXT: str r2, [sp] @ 4-byte Spill
; CHECK-NEXT: .LBB2_2: @ %while.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: str r1, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: asrs r2, r4, #31
; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: ldr r1, [r1]
; CHECK-NEXT: muls r1, r3, r1
; CHECK-NEXT: adds r4, r4, r1
; CHECK-NEXT: adc.w r1, r2, r1, asr #31
; CHECK-NEXT: adds.w r2, r4, #-2147483648
; CHECK-NEXT: ldrd r2, r4, [r8]
; CHECK-NEXT: adc r5, r1, #0
; CHECK-NEXT: ldr r2, [r0]
; CHECK-NEXT: asrs r5, r4, #31
; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: muls r2, r3, r2
; CHECK-NEXT: adds r4, r4, r2
; CHECK-NEXT: adc.w r2, r5, r2, asr #31
; CHECK-NEXT: ldr.w r5, [r9, #4]
; CHECK-NEXT: adds.w r4, r4, #-2147483648
; CHECK-NEXT: adc r1, r2, #0
; CHECK-NEXT: str r1, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: smull r5, r6, r5, r8
; CHECK-NEXT: ldr.w r2, [r9]
; CHECK-NEXT: asrs r4, r1, #31
; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: smull r4, r2, r4, r9
; CHECK-NEXT: asrs r1, r5, #31
; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: subs r4, r5, r4
; CHECK-NEXT: sbcs r1, r2
; CHECK-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: adds.w r10, r4, #-2147483648
; CHECK-NEXT: adc r1, r1, #0
; CHECK-NEXT: ldr r4, [r2, #-4]
; CHECK-NEXT: subs r5, r1, r5
; CHECK-NEXT: sbcs r4, r6
; CHECK-NEXT: adds.w r6, r5, #-2147483648
; CHECK-NEXT: adc r5, r4, #0
; CHECK-NEXT: ldr r4, [r0, #-4]
; CHECK-NEXT: muls r4, r3, r4
; CHECK-NEXT: adds r3, #4
; CHECK-NEXT: adds.w r12, r4, #-2147483648
; CHECK-NEXT: asr.w r5, r4, #31
; CHECK-NEXT: ldr r4, [r6]
; CHECK-NEXT: adc r5, r5, #0
; CHECK-NEXT: mul r2, r4, r0
; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: adds.w r0, r4, #-2147483648
; CHECK-NEXT: asr.w r1, r4, #31
; CHECK-NEXT: ldr.w r4, [r10]
; CHECK-NEXT: adc r1, r1, #0
; CHECK-NEXT: mul r2, r4, r12
; CHECK-NEXT: add.w r12, r12, #4
; CHECK-NEXT: add.w r2, r2, #-2147483648
; CHECK-NEXT: asrl r12, r5, r2
; CHECK-NEXT: smull r2, r5, r4, r12
; CHECK-NEXT: lsll r2, r5, #30
; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: asr.w r11, r5, #31
; CHECK-NEXT: mov r12, r5
; CHECK-NEXT: lsll r12, r11, r4
; CHECK-NEXT: mul r2, r2, r9
; CHECK-NEXT: lsrl r12, r11, #2
; CHECK-NEXT: adds r2, #2
; CHECK-NEXT: lsll r12, r11, r2
; CHECK-NEXT: asrl r0, r1, r2
; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
; CHECK-NEXT: add.w r5, r12, #-2147483648
; CHECK-NEXT: asrl r10, r1, r5
; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: lsrl r10, r1, #2
; CHECK-NEXT: movs r1, #2
; CHECK-NEXT: mov r9, r10
; CHECK-NEXT: str.w r10, [r1]
; CHECK-NEXT: ldr r1, [r8], #-4
; CHECK-NEXT: mls r5, r1, r4, r5
; CHECK-NEXT: adds.w r4, r5, #-2147483648
; CHECK-NEXT: asr.w r1, r5, #31
; CHECK-NEXT: smull r0, r1, r4, r0
; CHECK-NEXT: lsll r0, r1, #30
; CHECK-NEXT: asr.w r11, r1, #31
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: lsll r0, r11, r4
; CHECK-NEXT: lsrl r0, r11, #2
; CHECK-NEXT: mul r1, r1, r8
; CHECK-NEXT: adds r1, #2
; CHECK-NEXT: lsll r0, r11, r1
; CHECK-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: add.w r0, r0, #-2147483648
; CHECK-NEXT: asrl r6, r5, r0
; CHECK-NEXT: movs r0, #2
; CHECK-NEXT: lsrl r6, r5, #2
; CHECK-NEXT: str r6, [r0]
; CHECK-NEXT: mov r8, r6
; CHECK-NEXT: ldr r0, [r9], #-4
; CHECK-NEXT: mls r0, r0, r4, r1
; CHECK-NEXT: adds.w r4, r0, #-2147483648
; CHECK-NEXT: asr.w r1, r0, #31
; CHECK-NEXT: adc r1, r1, #0
; CHECK-NEXT: lsrl r4, r1, #2
; CHECK-NEXT: rsbs r1, r4, #0
; CHECK-NEXT: str r1, [r2]
; CHECK-NEXT: str r1, [r6, #-4]
; CHECK-NEXT: adds r6, #4
; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: adds r1, #4
; CHECK-NEXT: rsbs r0, r4, #0
; CHECK-NEXT: str r0, [r2]
; CHECK-NEXT: str r0, [r10, #-4]
; CHECK-NEXT: add.w r10, r10, #4
; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: le lr, .LBB2_2
; CHECK-NEXT: .LBB2_3: @ %while.end
; CHECK-NEXT: add sp, #16
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1350,34 +1350,34 @@ define void @arm_biquad_cascade_df2T_f16(ptr nocapture readonly %S, ptr nocaptur
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: ldrd r6, r12, [r0, #4]
; CHECK-NEXT: ldrd r12, r6, [r0, #4]
; CHECK-NEXT: ldrb.w r9, [r0]
; CHECK-NEXT: vldr.16 s0, .LCPI17_0
; CHECK-NEXT: lsr.w r8, r3, #1
; CHECK-NEXT: b .LBB17_3
; CHECK-NEXT: .LBB17_1: @ %if.else
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
; CHECK-NEXT: vmovx.f16 s5, s4
; CHECK-NEXT: vstr.16 s4, [r6]
; CHECK-NEXT: vstr.16 s4, [r12]
; CHECK-NEXT: .LBB17_2: @ %if.end
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
; CHECK-NEXT: vstr.16 s5, [r6, #2]
; CHECK-NEXT: add.w r12, r12, #10
; CHECK-NEXT: vstr.16 s5, [r12, #2]
; CHECK-NEXT: adds r6, #10
; CHECK-NEXT: subs.w r9, r9, #1
; CHECK-NEXT: add.w r6, r6, #4
; CHECK-NEXT: add.w r12, r12, #4
; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: beq .LBB17_8
; CHECK-NEXT: .LBB17_3: @ %do.body
; CHECK-NEXT: @ =>This Loop Header: Depth=1
; CHECK-NEXT: @ Child Loop BB17_5 Depth 2
; CHECK-NEXT: vldrh.u16 q2, [r12]
; CHECK-NEXT: vldrh.u16 q2, [r6]
; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov q4, q2
; CHECK-NEXT: vshlc q4, r5, #16
; CHECK-NEXT: vldrh.u16 q3, [r12, #4]
; CHECK-NEXT: vldrh.u16 q3, [r6, #4]
; CHECK-NEXT: vmov q5, q3
; CHECK-NEXT: vshlc q5, r5, #16
; CHECK-NEXT: vldrh.u16 q1, [r6]
; CHECK-NEXT: vldrh.u16 q1, [r12]
; CHECK-NEXT: vmov.f32 s5, s1
; CHECK-NEXT: mov r5, r2
; CHECK-NEXT: wls lr, r8, .LBB17_6
Expand Down Expand Up @@ -1414,7 +1414,7 @@ define void @arm_biquad_cascade_df2T_f16(ptr nocapture readonly %S, ptr nocaptur
; CHECK-NEXT: vfma.f16 q1, q3, r0
; CHECK-NEXT: strh r0, [r5]
; CHECK-NEXT: vmovx.f16 s2, s4
; CHECK-NEXT: vstr.16 s2, [r6]
; CHECK-NEXT: vstr.16 s2, [r12]
; CHECK-NEXT: b .LBB17_2
; CHECK-NEXT: .LBB17_8: @ %do.end
; CHECK-NEXT: vpop {d8, d9, d10, d11}
Expand Down

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