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[RISCV][GISel] Select trap and debugtrap. (#73171)
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llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py | ||
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \ | ||
# RUN: -verify-machineinstrs %s -o - | FileCheck %s | ||
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \ | ||
# RUN: -verify-machineinstrs %s -o - | FileCheck %s | ||
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--- | ||
name: test_trap | ||
legalized: true | ||
regBankSelected: true | ||
tracksRegLiveness: true | ||
body: | | ||
bb.1: | ||
; CHECK-LABEL: name: test_trap | ||
; CHECK: UNIMP | ||
; CHECK-NEXT: PseudoRET | ||
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap) | ||
PseudoRET | ||
... | ||
--- | ||
name: test_debugtrap | ||
legalized: true | ||
regBankSelected: true | ||
tracksRegLiveness: true | ||
body: | | ||
bb.1: | ||
; CHECK-LABEL: name: test_debugtrap | ||
; CHECK: EBREAK | ||
; CHECK-NEXT: PseudoRET | ||
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.debugtrap) | ||
PseudoRET | ||
... |