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[RISCV][GISel] Select trap and debugtrap. #73171
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@llvm/pr-subscribers-llvm-globalisel @llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesFull diff: https://github.com/llvm/llvm-project/pull/73171.diff 2 Files Affected:
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 3c72269d1e00c2f..791ce7a855d9888 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -72,6 +72,8 @@ class RISCVInstructionSelector : public InstructionSelector {
MachineRegisterInfo &MRI) const;
bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) const;
+ bool selectIntrinsicWithSideEffects(MachineInstr &I, MachineIRBuilder &MIB,
+ MachineRegisterInfo &MRI);
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
ComplexRendererFns selectAddrRegImm(MachineOperand &Root) const;
@@ -564,6 +566,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
return selectSelect(MI, MIB, MRI);
case TargetOpcode::G_FCMP:
return selectFPCompare(MI, MIB, MRI);
+ case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
+ return selectIntrinsicWithSideEffects(MI, MIB, MRI);
default:
return false;
}
@@ -1099,6 +1103,27 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI,
return true;
}
+bool RISCVInstructionSelector::selectIntrinsicWithSideEffects(
+ MachineInstr &I, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) {
+ // Find the intrinsic ID.
+ unsigned IntrinID = cast<GIntrinsic>(I).getIntrinsicID();
+
+ // Select the instruction.
+ switch (IntrinID) {
+ default:
+ return false;
+ case Intrinsic::trap:
+ MIB.buildInstr(RISCV::UNIMP, {}, {});
+ break;
+ case Intrinsic::debugtrap:
+ MIB.buildInstr(RISCV::EBREAK, {}, {});
+ break;
+ }
+
+ I.eraseFromParent();
+ return true;
+}
+
namespace llvm {
InstructionSelector *
createRISCVInstructionSelector(const RISCVTargetMachine &TM,
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir
new file mode 100644
index 000000000000000..11789a030e6fac0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir
@@ -0,0 +1,34 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: test_trap
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: test_trap
+ ; CHECK: UNIMP
+ ; CHECK-NEXT: PseudoRET
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
+ PseudoRET
+
+...
+---
+name: test_debugtrap
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: test_debugtrap
+ ; CHECK: EBREAK
+ ; CHECK-NEXT: PseudoRET
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.debugtrap)
+ PseudoRET
+
+...
|
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LGTM with one minor comment.
@@ -1099,6 +1103,27 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI, | |||
return true; | |||
} | |||
|
|||
bool RISCVInstructionSelector::selectIntrinsicWithSideEffects( |
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assert (TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
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Doesn't the cast to GIntrinsic already take care of that?
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I think it will pass in the G_INTRINSIC, G_INTRINSIC_CONVERGENT, and G_INTRINSIC_CONVERGENT_W_WIDE_EFFECTS too, but it shouldn't.
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