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[RISCV] Add scalable offset under very large stack size.
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If the stack size is larger than 12 bits, we have to use a scratch
register to store the stack size. Before we introduce the scalable stack
offset, we could simplify

%0 = ADDI %stack.0, 0

=>

%scratch = ... # sequence of instructions to move the offset into
%%scratch
%0 = ADD %fp, %scratch

However, if the offset contains scalable part, we need to consider it.

%0 = ADDI %stack.0, 0

=>

%scratch = ... # sequence of instructions to move the offset into
%%scratch
%scratch = ADD %fp, %scratch
%scalable_offset = ... # sequence of instructions for vscaled-offset.
%0 = ADD/SUB %scratch, %scalable_offset

Differential Revision: https://reviews.llvm.org/D100035
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Hsiangkai committed Apr 8, 2021
1 parent b8cd668 commit ba72bde
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Showing 2 changed files with 10 additions and 1 deletion.
9 changes: 8 additions & 1 deletion llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -213,7 +213,7 @@ void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// Modify Offset and FrameReg appropriately
Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
TII->movImm(MBB, II, DL, ScratchReg, Offset.getFixed());
if (MI.getOpcode() == RISCV::ADDI) {
if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) {
BuildMI(MBB, II, DL, TII->get(RISCV::ADD), MI.getOperand(0).getReg())
.addReg(FrameReg)
.addReg(ScratchReg, RegState::Kill);
Expand Down Expand Up @@ -258,6 +258,13 @@ void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
TII->getVLENFactoredAmount(MF, MBB, II, ScalableValue);

// 2. Calculate address: FrameReg + result of multiply
if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) {
BuildMI(MBB, II, DL, TII->get(Opc), MI.getOperand(0).getReg())
.addReg(FrameReg, getKillRegState(FrameRegIsKill))
.addReg(FactorRegister, RegState::Kill);
MI.eraseFromParent();
return;
}
Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
BuildMI(MBB, II, DL, TII->get(Opc), VL)
.addReg(FrameReg, getKillRegState(FrameRegIsKill))
Expand Down
2 changes: 2 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,8 @@ body: |
; CHECK: $x10 = LUI 1048575
; CHECK: $x10 = ADDIW killed $x10, 1824
; CHECK: $x10 = ADD $x8, killed $x10
; CHECK: $x11 = PseudoReadVLENB
; CHECK: $x10 = SUB killed $x10, killed $x11
; CHECK: VS1R_V killed renamable $v25, killed renamable $x10
; CHECK: $x10 = PseudoReadVLENB
; CHECK: $x2 = ADD $x2, killed $x10
Expand Down

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