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[machinesink] add testcase for more sinking - NFC
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | ||
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ | ||
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs < %s | FileCheck %s | ||
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define signext i32 @foo(i32 signext %0, i32 signext %1, i32* %2, i32* %3, i32 signext %4) { | ||
; CHECK-LABEL: foo: | ||
; CHECK: # %bb.0: | ||
; CHECK-NEXT: cmpwi r7, 1 | ||
; CHECK-NEXT: blt cr0, .LBB0_8 | ||
; CHECK-NEXT: # %bb.1: | ||
; CHECK-NEXT: addi r4, r5, -4 | ||
; CHECK-NEXT: addi r8, r6, -4 | ||
; CHECK-NEXT: clrldi r7, r7, 32 | ||
; CHECK-NEXT: li r5, 0 | ||
; CHECK-NEXT: mtctr r7 | ||
; CHECK-NEXT: lis r7, -30584 | ||
; CHECK-NEXT: li r6, 0 | ||
; CHECK-NEXT: cmplwi r3, 3 | ||
; CHECK-NEXT: cmplwi cr1, r3, 1 | ||
; CHECK-NEXT: ori r7, r7, 34953 | ||
; CHECK-NEXT: b .LBB0_4 | ||
; CHECK-NEXT: .p2align 4 | ||
; CHECK-NEXT: .LBB0_2: | ||
; CHECK-NEXT: mulhwu r9, r6, r7 | ||
; CHECK-NEXT: srwi r9, r9, 4 | ||
; CHECK-NEXT: mulli r9, r9, 30 | ||
; CHECK-NEXT: sub r9, r6, r9 | ||
; CHECK-NEXT: .LBB0_3: | ||
; CHECK-NEXT: addi r6, r6, 1 | ||
; CHECK-NEXT: add r9, r9, r5 | ||
; CHECK-NEXT: stw r9, 4(r8) | ||
; CHECK-NEXT: mr r8, r3 | ||
; CHECK-NEXT: bdz .LBB0_8 | ||
; CHECK-NEXT: .LBB0_4: | ||
; CHECK-NEXT: lwzu r9, 4(r4) | ||
; CHECK-NEXT: addi r3, r8, 4 | ||
; CHECK-NEXT: add r5, r9, r5 | ||
; CHECK-NEXT: beq cr0, .LBB0_7 | ||
; CHECK-NEXT: # %bb.5: | ||
; CHECK-NEXT: bne cr1, .LBB0_2 | ||
; CHECK-NEXT: # %bb.6: | ||
; CHECK-NEXT: slwi r9, r6, 1 | ||
; CHECK-NEXT: b .LBB0_3 | ||
; CHECK-NEXT: .p2align 4 | ||
; CHECK-NEXT: .LBB0_7: | ||
; CHECK-NEXT: addi r9, r6, 100 | ||
; CHECK-NEXT: b .LBB0_3 | ||
; CHECK-NEXT: .LBB0_8: | ||
; CHECK-NEXT: li r3, 0 | ||
; CHECK-NEXT: blr | ||
%6 = icmp sgt i32 %4, 0 | ||
br i1 %6, label %7, label %9 | ||
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7: ; preds = %5 | ||
%8 = zext i32 %4 to i64 | ||
br label %10 | ||
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9: ; preds = %25, %5 | ||
ret i32 undef | ||
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10: ; preds = %7, %25 | ||
%11 = phi i64 [ 0, %7 ], [ %29, %25 ] | ||
%12 = phi i32 [ 0, %7 ], [ %30, %25 ] | ||
%13 = phi i32 [ 0, %7 ], [ %16, %25 ] | ||
%14 = getelementptr inbounds i32, i32* %2, i64 %11 | ||
%15 = load i32, i32* %14, align 4 | ||
%16 = add nsw i32 %15, %13 | ||
switch i32 %0, label %22 [ | ||
i32 1, label %17 | ||
i32 3, label %20 | ||
] | ||
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17: ; preds = %10 | ||
%18 = trunc i64 %11 to i32 | ||
%19 = shl i32 %18, 1 | ||
br label %25 | ||
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20: ; preds = %10 | ||
%21 = add nuw nsw i32 %12, 100 | ||
br label %25 | ||
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22: ; preds = %10 | ||
%23 = trunc i64 %11 to i32 | ||
%24 = urem i32 %23, 30 | ||
br label %25 | ||
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25: ; preds = %22, %20, %17 | ||
%26 = phi i32 [ %24, %22 ], [ %21, %20 ], [ %19, %17 ] | ||
%27 = add nsw i32 %26, %16 | ||
%28 = getelementptr inbounds i32, i32* %3, i64 %11 | ||
store i32 %27, i32* %28, align 4 | ||
%29 = add nuw nsw i64 %11, 1 | ||
%30 = add nuw nsw i32 %12, 1 | ||
%31 = icmp eq i64 %29, %8 | ||
br i1 %31, label %9, label %10 | ||
} | ||
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