[AMDGPU] Increase instruction cache line size to 128 bytes for GFX11

Differential Revision: https://reviews.llvm.org/D128189
llvm · Jun 20, 2022 · d7762a3 · d7762a3
1 parent b8e32e8
commit d7762a3
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
@@ -301,7 +301,7 @@ bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
   uint32_t Encoded_pad = Encoded_s_code_end;
 
   // Instruction cache line size in bytes.
-  const unsigned Log2CacheLineSize = 6;
+  const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
   const unsigned CacheLineSize = 1u << Log2CacheLineSize;
 
   // Extra padding amount in bytes to support prefetch mode 3.
@@ -824,7 +824,7 @@ bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
   uint32_t Encoded_pad = Encoded_s_code_end;
 
   // Instruction cache line size in bytes.
-  const unsigned Log2CacheLineSize = 6;
+  const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
   const unsigned CacheLineSize = 1u << Log2CacheLineSize;
 
   // Extra padding amount in bytes to support prefetch mode 3.

diff --git a/llvm/test/CodeGen/AMDGPU/s_code_end.ll b/llvm/test/CodeGen/AMDGPU/s_code_end.ll
@@ -41,10 +41,10 @@ define amdgpu_kernel void @a_kernel2() #0 {
 ; GCN-ASM-NEXT:   [[END_LABEL3:\.Lfunc_end.*]]:
 ; GCN-ASM-NEXT:           .size   a_function, [[END_LABEL3]]-a_function
 ; GFX10END-ASM:           .p2alignl 6, 3214868480
-; GFX11END-ASM:           .p2alignl 6, 3214868480
+; GFX11END-ASM:           .p2alignl 7, 3214868480
 ; GFX90AEND-ASM:          .p2alignl 6, 3212836864
 ; GFX10END-ASM-NEXT:      .fill 48, 4, 3214868480
-; GFX11END-ASM-NEXT:      .fill 48, 4, 3214868480
+; GFX11END-ASM-NEXT:      .fill 96, 4, 3214868480
 ; GFX90AEND-ASM-NEXT:     .fill 256, 4, 3212836864
 ; GFX10NOEND-NOT:         .fill
 ; GFX11NOEND-NOT:         .fill