[RISCV][MacroFusion] Improve fusion in pre-RA

[zxc12523]

#79425 has adopted TableGen-based macro fusion.

And it will generate RISCVGenMacroFusion.inc.

bool isTuneAUIPCADDIFusion(
    const TargetInstrInfo &TII,
    const TargetSubtargetInfo &STI,
    const MachineInstr *FirstMI,
    const MachineInstr &SecondMI) {
  auto &MRI = SecondMI.getMF()->getRegInfo();
  {
    const MachineInstr *MI = &SecondMI;
    if (( MI->getOpcode() != RISCV::ADDI ))
      return false;
  }
  if (!FirstMI)
    return true;
  {
    const MachineInstr *MI = FirstMI;
    if (( MI->getOpcode() != RISCV::AUIPC ))
      return false;
  }
  {
    const MachineInstr *MI = &SecondMI;
    if (!(
        MI->getOperand(0).getReg().isVirtual()
        || MI->getOperand(0).getReg() == MI->getOperand(1).getReg()
      ))
      return false;
  }
  {
    Register FirstDest = FirstMI->getOperand(0).getReg();
    if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
      return false;
  }
  if (!(FirstMI->getOperand(0).isReg() &&
        SecondMI.getOperand(1).isReg() &&
        FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
    return false;
  return true;
}

My question is, is it possible to check FirstMI->getOperand(0).getReg() == SecondMI.getOperand(2).getReg() when these two regs are virtual and the second inst is commutative?

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: None (zxc12523)

#79425 has adopted TableGen-based macro fusion.

And it will generate RISCVGenMacroFusion.inc.

bool isTuneAUIPCADDIFusion(
    const TargetInstrInfo &TII,
    const TargetSubtargetInfo &STI,
    const MachineInstr *FirstMI,
    const MachineInstr &SecondMI) {
  auto &MRI = SecondMI.getMF()->getRegInfo();
  {
    const MachineInstr *MI = &SecondMI;
    if (( MI->getOpcode() != RISCV::ADDI ))
      return false;
  }
  if (!FirstMI)
    return true;
  {
    const MachineInstr *MI = FirstMI;
    if (( MI->getOpcode() != RISCV::AUIPC ))
      return false;
  }
  {
    const MachineInstr *MI = &SecondMI;
    if (!(
        MI->getOperand(0).getReg().isVirtual()
        || MI->getOperand(0).getReg() == MI->getOperand(1).getReg()
      ))
      return false;
  }
  {
    Register FirstDest = FirstMI->getOperand(0).getReg();
    if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
      return false;
  }
  if (!(FirstMI->getOperand(0).isReg() &&
        SecondMI.getOperand(1).isReg() &&
        FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
    return false;
  return true;
}

My question is, is it possible to check FirstMI->getOperand(0).getReg() == SecondMI.getOperand(2).getReg() when these two regs are virtual and the second inst is commutative?

[wangpc-pp]

is it possible to check FirstMI->getOperand(0).getReg() == SecondMI.getOperand(2).getReg() when these two regs are virtual and the second inst is commutative?

Yes, it can be set via adding a TieReg<0, 2>.

This can be done automatically, I will create a PR for this. Thanks for reporting!

[zxc12523]

Thanks for your response! Are there any tablegen learning materials or source code reading tools I can use? I am a newbie and I want to learn more about this topic.

[wangpc-pp]

Thanks for your response! Are there any tablegen learning materials or source code reading tools I can use? I am a newbie and I want to learn more about this topic.

You mean the TableGen-based macro fusion? I have some links that you can refer to:

• [RFC] TableGen-driven MacroFusion predicators generator. This is the RFC, but the implementation is a little different now after reviewing and some refactors.
• [RISCV] Use TableGen-based macro fusion #72224 (comment). This is the whole patchset of TableGen-based macro fusion.

Some code links:

• llvm-project/llvm/include/llvm/Target/TargetSchedule.td

  Lines 585 to 699 in 8be39b3

  	// The target instruction that FusionPredicate will be evaluated on.
  	class FusionTarget;
  	def first_fusion_target : FusionTarget;
  	def second_fusion_target : FusionTarget;
  	def both_fusion_target : FusionTarget;
  	// Base class of FusionPredicate, etc. The avaliable variables are:
  	// * const TargetInstrInfo &TII
  	// * const TargetSubtargetInfo &STI
  	// * const MachineRegisterInfo &MRI
  	// * const MachineInstr *FirstMI
  	// * const MachineInstr &SecondMI
  	class FusionPredicate<FusionTarget target> {
  	FusionTarget Target = target;
  	}
  	class FirstFusionPredicate: FusionPredicate<first_fusion_target>;
  	class SecondFusionPredicate: FusionPredicate<second_fusion_target>;
  	class BothFusionPredicate: FusionPredicate<both_fusion_target>;
  	// FusionPredicate with raw code predicate.
  	class FusionPredicateWithCode<code pred> : FusionPredicate<both_fusion_target> {
  	code Predicate = pred;
  	}
  	// FusionPredicate with MCInstPredicate.
  	class FusionPredicateWithMCInstPredicate<FusionTarget target, MCInstPredicate pred>
  	: FusionPredicate<target> {
  	MCInstPredicate Predicate = pred;
  	}
  	class FirstFusionPredicateWithMCInstPredicate<MCInstPredicate pred>
  	: FusionPredicateWithMCInstPredicate<first_fusion_target, pred>;
  	class SecondFusionPredicateWithMCInstPredicate<MCInstPredicate pred>
  	: FusionPredicateWithMCInstPredicate<second_fusion_target, pred>;
  	// The pred will be applied on both firstMI and secondMI.
  	class BothFusionPredicateWithMCInstPredicate<MCInstPredicate pred>
  	: FusionPredicateWithMCInstPredicate<second_fusion_target, pred>;
  	// Tie firstOpIdx and secondOpIdx. The operand of `FirstMI` at position
  	// `firstOpIdx` should be the same as the operand of `SecondMI` at position
  	// `secondOpIdx`.
  	class TieReg<int firstOpIdx, int secondOpIdx> : BothFusionPredicate {
  	int FirstOpIdx = firstOpIdx;
  	int SecondOpIdx = secondOpIdx;
  	}
  	// A predicate for wildcard. The generated code will be like:
  	// ```
  	// if (!FirstMI)
  	// return ReturnValue;
  	// ```
  	class WildcardPred<bit ret> : FirstFusionPredicate {
  	bit ReturnValue = ret;
  	}
  	def WildcardFalse : WildcardPred<0>;
  	def WildcardTrue : WildcardPred<1>;
  	// Indicates that the destination register of `FirstMI` should have one use if
  	// it is a virtual register.
  	class OneUsePred : FirstFusionPredicate;
  	def OneUse : OneUsePred;
  	// Handled by MacroFusionPredicatorEmitter backend.
  	// The generated predicator will be like:
  	// ```
  	// bool isNAME(const TargetInstrInfo &TII,
  	// const TargetSubtargetInfo &STI,
  	// const MachineInstr *FirstMI,
  	// const MachineInstr &SecondMI) {
  	// auto &MRI = SecondMI.getMF()->getRegInfo();
  	// /* Predicates */
  	// return true;
  	// }
  	// ```
  	class Fusion<string name, string fieldName, string desc, list<FusionPredicate> predicates>
  	: SubtargetFeature<name, fieldName, "true", desc> {
  	list<FusionPredicate> Predicates = predicates;
  	}
  	// The generated predicator will be like:
  	// ```
  	// bool isNAME(const TargetInstrInfo &TII,
  	// const TargetSubtargetInfo &STI,
  	// const MachineInstr *FirstMI,
  	// const MachineInstr &SecondMI) {
  	// auto &MRI = SecondMI.getMF()->getRegInfo();
  	// /* Prolog */
  	// /* Predicate for `SecondMI` */
  	// /* Wildcard */
  	// /* Predicate for `FirstMI` */
  	// /* Check One Use */
  	// /* Tie registers */
  	// /* Epilog */
  	// return true;
  	// }
  	// ```
  	class SimpleFusion<string name, string fieldName, string desc,
  	MCInstPredicate firstPred, MCInstPredicate secondPred,
  	list<FusionPredicate> prolog = [],
  	list<FusionPredicate> epilog = []>
  	: Fusion<name, fieldName, desc,
  	!listconcat(
  	prolog,
  	[
  	SecondFusionPredicateWithMCInstPredicate<secondPred>,
  	WildcardTrue,
  	FirstFusionPredicateWithMCInstPredicate<firstPred>,
  	SecondFusionPredicateWithMCInstPredicate<
  	CheckAny<[
  	CheckIsVRegOperand<0>,
  	CheckSameRegOperand<0, 1>
  	]>>,
  	OneUse,
  	TieReg<0, 1>,
  	],
  	epilog)>;

  These are the TableGen definitions. I think they are expressive but not so easy to use (I'm continuing to do some improvements).
• https://github.com/llvm/llvm-project/blob/main/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp. This is the TableGen backend that generates these predicators.