[RISCV] Use TableGen-based macro fusion #72224
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added
backend:ARM
backend:AArch64
backend:AMDGPU
backend:RISC-V
backend:X86
mc
|
@llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-mc Author: Wang Pengcheng (wangpc-pp) ChangesWe convert LUIADDI macro fusion to TableGen. For test, I added This PR is stacked on ##72219, #72222, #72223 Patch is 49.00 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/72224.diff 34 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/MacroFusion.h b/llvm/include/llvm/CodeGen/MacroFusion.h
index ea2c7a5faae385a..a97f776335368c7 100644
--- a/llvm/include/llvm/CodeGen/MacroFusion.h
+++ b/llvm/include/llvm/CodeGen/MacroFusion.h
@@ -14,8 +14,8 @@
#ifndef LLVM_CODEGEN_MACROFUSION_H
#define LLVM_CODEGEN_MACROFUSION_H
-#include <functional>
#include <memory>
+#include <vector>
namespace llvm {
@@ -29,10 +29,10 @@ class SUnit;
/// Check if the instr pair, FirstMI and SecondMI, should be fused
/// together. Given SecondMI, when FirstMI is unspecified, then check if
/// SecondMI may be part of a fused pair at all.
-using ShouldSchedulePredTy = std::function<bool(const TargetInstrInfo &TII,
- const TargetSubtargetInfo &TSI,
- const MachineInstr *FirstMI,
- const MachineInstr &SecondMI)>;
+using MacroFusionPredTy = bool (*)(const TargetInstrInfo &TII,
+ const TargetSubtargetInfo &STI,
+ const MachineInstr *FirstMI,
+ const MachineInstr &SecondMI);
/// Checks if the number of cluster edges between SU and its predecessors is
/// less than FuseLimit
@@ -48,15 +48,15 @@ bool fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU,
/// Create a DAG scheduling mutation to pair instructions back to back
/// for instructions that benefit according to the target-specific
-/// shouldScheduleAdjacent predicate function.
+/// predicate functions.
std::unique_ptr<ScheduleDAGMutation>
-createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent);
+createMacroFusionDAGMutation(std::vector<MacroFusionPredTy> Predicates);
/// Create a DAG scheduling mutation to pair branch instructions with one
/// of their predecessors back to back for instructions that benefit according
-/// to the target-specific shouldScheduleAdjacent predicate function.
+/// to the target-specific predicate functions.
std::unique_ptr<ScheduleDAGMutation>
-createBranchMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent);
+createBranchMacroFusionDAGMutation(std::vector<MacroFusionPredTy> Predicates);
} // end namespace llvm
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index 55ef95c28543190..7c76293f3e5eaea 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -16,6 +16,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/CodeGen/PBQPRAConstraint.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/IR/GlobalValue.h"
@@ -323,6 +324,9 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
/// helps removing redundant copies generated by register allocator when
/// handling complex eviction chains.
virtual bool enableSpillageCopyElimination() const { return false; }
+
+ /// Get the list of MacroFusion predicates.
+ virtual std::vector<MacroFusionPredTy> getMacroFusions() const { return {}; }
};
} // end namespace llvm
diff --git a/llvm/include/llvm/MC/MCSchedule.h b/llvm/include/llvm/MC/MCSchedule.h
index 98ebe42cfd133b5..aa187e5cb400672 100644
--- a/llvm/include/llvm/MC/MCSchedule.h
+++ b/llvm/include/llvm/MC/MCSchedule.h
@@ -14,6 +14,7 @@
#ifndef LLVM_MC_MCSCHEDULE_H
#define LLVM_MC_MCSCHEDULE_H
+#include "llvm/ADT/Bitset.h"
#include "llvm/Config/llvm-config.h"
#include "llvm/Support/DataTypes.h"
#include <cassert>
@@ -196,6 +197,9 @@ struct MCExtraProcessorInfo {
unsigned StoreQueueID;
};
+const unsigned MaxMacroFusions = 256;
+using MacroFusionBitset = Bitset<MaxMacroFusions>;
+
/// Machine model for scheduling, bundling, and heuristics.
///
/// The machine model directly provides basic information about the
@@ -325,9 +329,14 @@ struct MCSchedModel {
const InstrItinerary *InstrItineraries;
const MCExtraProcessorInfo *ExtraProcessorInfo;
+ const MacroFusionBitset *MacroFusionBits;
bool hasExtraProcessorInfo() const { return ExtraProcessorInfo; }
+ const MacroFusionBitset *getMacroFusionBits() const {
+ return MacroFusionBits;
+ }
+
unsigned getProcessorID() const { return ProcID; }
/// Does this machine model include instruction-level scheduling.
diff --git a/llvm/include/llvm/MC/MCSubtargetInfo.h b/llvm/include/llvm/MC/MCSubtargetInfo.h
index f172a799aa3331c..66fb6c9383272e1 100644
--- a/llvm/include/llvm/MC/MCSubtargetInfo.h
+++ b/llvm/include/llvm/MC/MCSubtargetInfo.h
@@ -120,6 +120,12 @@ class MCSubtargetInfo {
return FeatureBits[Feature];
}
+ bool hasMacroFusion(unsigned MacroFusion) const {
+ const MacroFusionBitset *MacroFusionBits =
+ CPUSchedModel->getMacroFusionBits();
+ return MacroFusionBits && MacroFusionBits->test(MacroFusion);
+ }
+
protected:
/// Initialize the scheduling model and feature bits.
///
@@ -295,6 +301,13 @@ class MCSubtargetInfo {
/// \return if target want to issue a prefetch in address space \p AS.
virtual bool shouldPrefetchAddressSpace(unsigned AS) const;
+
+ /// Enable macro fusion for this subtarget.
+ virtual bool enableMacroFusion() const {
+ const MacroFusionBitset *MacroFusionBits =
+ CPUSchedModel->getMacroFusionBits();
+ return MacroFusionBits && MacroFusionBits->any();
+ }
};
} // end namespace llvm
diff --git a/llvm/include/llvm/Target/TargetInstrPredicate.td b/llvm/include/llvm/Target/TargetInstrPredicate.td
index 9f2cde9d923050a..f7e6a390045b520 100644
--- a/llvm/include/llvm/Target/TargetInstrPredicate.td
+++ b/llvm/include/llvm/Target/TargetInstrPredicate.td
@@ -95,6 +95,12 @@ class MCOperandPredicate<int Index> : MCInstPredicate {
// Return true if machine operand at position `Index` is a register operand.
class CheckIsRegOperand<int Index> : MCOperandPredicate<Index>;
+// Return true if machine operand at position `Index` is a virtual register operand.
+class CheckIsVRegOperand<int Index> : MCOperandPredicate<Index>;
+
+// Return true if machine operand at position `Index` is not a virtual register operand.
+class CheckIsNotVirtualRegOperand<int Index> : CheckNot<CheckIsVRegOperand<Index>>;
+
// Return true if machine operand at position `Index` is an immediate operand.
class CheckIsImmOperand<int Index> : MCOperandPredicate<Index>;
diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td
index 949baa5d2105c45..ed07010dfb2d39f 100644
--- a/llvm/include/llvm/Target/TargetSchedule.td
+++ b/llvm/include/llvm/Target/TargetSchedule.td
@@ -53,6 +53,7 @@
include "llvm/Target/TargetItinerary.td"
class Predicate; // Forward def
+class MacroFusion;
// DAG operator that interprets the DAG args as Instruction defs.
def instrs;
@@ -122,6 +123,9 @@ class SchedMachineModel {
// using intervals via ResourceSegments (see
// llvm/include/llvm/CodeGen/MachineScheduler.h).
bit EnableIntervals = false;
+
+ // List of MacroFusion.
+ list<MacroFusion> MacroFusions = [];
}
def NoSchedModel : SchedMachineModel {
@@ -469,6 +473,67 @@ class SchedAlias<SchedReadWrite match, SchedReadWrite alias> {
SchedMachineModel SchedModel = ?;
}
+// Base class of MacroFusionPredicate, etc. The avaliable variables are:
+// * const TargetInstrInfo &TII
+// * const TargetSubtargetInfo &STI
+// * const MachineRegisterInfo &MRI
+// * const MachineInstr *FirstMI
+// * const MachineInstr &SecondMI
+class MacroFusionPredicateBase;
+
+// MacroFusionPredicate with raw code predicate.
+class MacroFusionPredicate<code pred> : MacroFusionPredicateBase {
+ code Predicate = pred;
+}
+
+// Binds firstOpIdx and secondOpIdx. The operand of `FirstMI` at position
+// `firstOpIdx` should be the same as the operand of `SenondMI` at position
+// `secondOpIdx`.
+class BindReg<int firstOpIdx, int secondOpIdx> : MacroFusionPredicateBase {
+ int FirstOpIdx = firstOpIdx;
+ int SecondOpIdx = secondOpIdx;
+}
+
+// A predicate for wildcard. The generated code will be like:
+// ```
+// if (!FirstMI)
+// return ReturnValue;
+// ```
+class WildcardPred<bit ret> : MacroFusionPredicateBase {
+ bit ReturnValue = ret;
+}
+def WildcardFalse : WildcardPred<0>;
+def WildcardTrue : WildcardPred<1>;
+
+// Indicates that the destination register of `FirstMI` should be have one
+// use if it is an virtual register.
+class OneUsePred : MacroFusionPredicateBase;
+def OneUse : OneUsePred;
+
+// Handled by MacroFusionPredicatorEmitter backend.
+// The generated predicator will be like:
+// ```
+// bool isNAME(const TargetInstrInfo &TII,
+// const TargetSubtargetInfo &STI,
+// const MachineInstr *FirstMI,
+// const MachineInstr &SecondMI) {
+// auto &MRI = SecondMI.getMF()->getRegInfo();
+// /* Prolog */
+// /* Predicate for `FirstMI` */
+// /* Predicate for `SecondMI` */
+// /* Epilog */
+// return true;
+// }
+// ```
+class MacroFusion<MCInstPredicate first, MCInstPredicate second,
+ list<MacroFusionPredicateBase> prolog = [],
+ list<MacroFusionPredicateBase> epilog = []> {
+ MCInstPredicate First = first;
+ MCInstPredicate Second = second;
+ list<MacroFusionPredicateBase> Prolog = prolog;
+ list<MacroFusionPredicateBase> Epilog = epilog;
+}
+
// Allow the definition of processor register files for register renaming
// purposes.
//
diff --git a/llvm/lib/CodeGen/MacroFusion.cpp b/llvm/lib/CodeGen/MacroFusion.cpp
index fa5df68b8abcc0f..63ea53f9cc32f97 100644
--- a/llvm/lib/CodeGen/MacroFusion.cpp
+++ b/llvm/lib/CodeGen/MacroFusion.cpp
@@ -137,19 +137,35 @@ namespace {
/// Post-process the DAG to create cluster edges between instrs that may
/// be fused by the processor into a single operation.
class MacroFusion : public ScheduleDAGMutation {
- ShouldSchedulePredTy shouldScheduleAdjacent;
+ std::vector<MacroFusionPredTy> Predicates;
bool FuseBlock;
bool scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU);
public:
- MacroFusion(ShouldSchedulePredTy shouldScheduleAdjacent, bool FuseBlock)
- : shouldScheduleAdjacent(shouldScheduleAdjacent), FuseBlock(FuseBlock) {}
+ MacroFusion(std::vector<MacroFusionPredTy> Predicates, bool FuseBlock)
+ : Predicates(Predicates), FuseBlock(FuseBlock) {}
void apply(ScheduleDAGInstrs *DAGInstrs) override;
+
+ bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
+ const TargetSubtargetInfo &STI,
+ const MachineInstr *FirstMI,
+ const MachineInstr &SecondMI);
};
} // end anonymous namespace
+bool MacroFusion::shouldScheduleAdjacent(const TargetInstrInfo &TII,
+ const TargetSubtargetInfo &STI,
+ const MachineInstr *FirstMI,
+ const MachineInstr &SecondMI) {
+ for (MacroFusionPredTy Predicate : Predicates) {
+ if (Predicate(TII, STI, FirstMI, SecondMI))
+ return true;
+ }
+ return false;
+}
+
void MacroFusion::apply(ScheduleDAGInstrs *DAG) {
if (FuseBlock)
// For each of the SUnits in the scheduling block, try to fuse the instr in
@@ -197,17 +213,16 @@ bool MacroFusion::scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU)
}
std::unique_ptr<ScheduleDAGMutation>
-llvm::createMacroFusionDAGMutation(
- ShouldSchedulePredTy shouldScheduleAdjacent) {
- if(EnableMacroFusion)
- return std::make_unique<MacroFusion>(shouldScheduleAdjacent, true);
+llvm::createMacroFusionDAGMutation(std::vector<MacroFusionPredTy> Predicates) {
+ if (EnableMacroFusion) {
+ return std::make_unique<MacroFusion>(Predicates, true);
+ }
return nullptr;
}
-std::unique_ptr<ScheduleDAGMutation>
-llvm::createBranchMacroFusionDAGMutation(
- ShouldSchedulePredTy shouldScheduleAdjacent) {
- if(EnableMacroFusion)
- return std::make_unique<MacroFusion>(shouldScheduleAdjacent, false);
+std::unique_ptr<ScheduleDAGMutation> llvm::createBranchMacroFusionDAGMutation(
+ std::vector<MacroFusionPredTy> Predicates) {
+ if (EnableMacroFusion)
+ return std::make_unique<MacroFusion>(Predicates, false);
return nullptr;
}
diff --git a/llvm/lib/MC/MCSchedule.cpp b/llvm/lib/MC/MCSchedule.cpp
index 990a693559a7776..19c36cb0e58d9c1 100644
--- a/llvm/lib/MC/MCSchedule.cpp
+++ b/llvm/lib/MC/MCSchedule.cpp
@@ -37,6 +37,7 @@ const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
0,
0,
nullptr,
+ nullptr,
nullptr};
int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
diff --git a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
index 05d60872bf51aca..8f46f3eabb3ef45 100644
--- a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
@@ -478,5 +478,5 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
std::unique_ptr<ScheduleDAGMutation>
llvm::createAArch64MacroFusionDAGMutation() {
- return createMacroFusionDAGMutation(shouldScheduleAdjacent);
+ return createMacroFusionDAGMutation({shouldScheduleAdjacent});
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp
index c15c94ee17f8b1d..b2b11d661523e9c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp
@@ -59,8 +59,8 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII_,
namespace llvm {
-std::unique_ptr<ScheduleDAGMutation> createAMDGPUMacroFusionDAGMutation () {
- return createMacroFusionDAGMutation(shouldScheduleAdjacent);
+std::unique_ptr<ScheduleDAGMutation> createAMDGPUMacroFusionDAGMutation() {
+ return createMacroFusionDAGMutation({shouldScheduleAdjacent});
}
} // end namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
index 29c9b9ccf27614f..0bddeeef9e9b1a3 100644
--- a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
@@ -142,10 +142,10 @@ namespace {
/// be turned into VOPD instructions
/// Greedily pairs instruction candidates. O(n^2) algorithm.
struct VOPDPairingMutation : ScheduleDAGMutation {
- ShouldSchedulePredTy shouldScheduleAdjacent; // NOLINT: function pointer
+ MacroFusionPredTy shouldScheduleAdjacent; // NOLINT: function pointer
VOPDPairingMutation(
- ShouldSchedulePredTy shouldScheduleAdjacent) // NOLINT: function pointer
+ MacroFusionPredTy shouldScheduleAdjacent) // NOLINT: function pointer
: shouldScheduleAdjacent(shouldScheduleAdjacent) {}
void apply(ScheduleDAGInstrs *DAG) override {
diff --git a/llvm/lib/Target/ARM/ARMMacroFusion.cpp b/llvm/lib/Target/ARM/ARMMacroFusion.cpp
index 38bf28ba8219b90..7de117925e464fe 100644
--- a/llvm/lib/Target/ARM/ARMMacroFusion.cpp
+++ b/llvm/lib/Target/ARM/ARMMacroFusion.cpp
@@ -62,8 +62,8 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
return false;
}
-std::unique_ptr<ScheduleDAGMutation> createARMMacroFusionDAGMutation () {
- return createMacroFusionDAGMutation(shouldScheduleAdjacent);
+std::unique_ptr<ScheduleDAGMutation> createARMMacroFusionDAGMutation() {
+ return createMacroFusionDAGMutation({shouldScheduleAdjacent});
}
} // end namespace llvm
diff --git a/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp b/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
index bf1c39a3a3a2d47..d6a4a5dd5faabae 100644
--- a/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
@@ -286,8 +286,8 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
namespace llvm {
-std::unique_ptr<ScheduleDAGMutation> createPowerPCMacroFusionDAGMutation () {
- return createMacroFusionDAGMutation(shouldScheduleAdjacent);
+std::unique_ptr<ScheduleDAGMutation> createPowerPCMacroFusionDAGMutation() {
+ return createMacroFusionDAGMutation({shouldScheduleAdjacent});
}
} // end namespace llvm
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index a0c3345ec1bbd7e..ac88cd49db4e4ba 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -5,6 +5,7 @@ set(LLVM_TARGET_DEFINITIONS RISCV.td)
tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
+tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
@@ -43,7 +44,6 @@ add_llvm_target(RISCVCodeGen
RISCVISelDAGToDAG.cpp
RISCVISelLowering.cpp
RISCVMachineFunctionInfo.cpp
- RISCVMacroFusion.cpp
RISCVMergeBaseOffset.cpp
RISCVOptWInstrs.cpp
RISCVPostRAExpandPseudoInsts.cpp
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
index 3cfddb530cdf630..f3f27efbee95f7d 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
@@ -48,6 +48,9 @@ std::unique_ptr<MCObjectTargetWriter> createRISCVELFObjectWriter(uint8_t OSABI,
#define GET_INSTRINFO_MC_HELPER_DECLS
#include "RISCVGenInstrInfo.inc"
+#define GET_MACRO_FUSION_ENUM
+#include "RISCVGenMacroFusion.inc"
+
#define GET_SUBTARGETINFO_ENUM
#include "RISCVGenSubtargetInfo.inc"
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index 4358a5b878e6316..dbc286288d2c897 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -236,7 +236,7 @@ InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI) {
// NOTE: We don't check for C extension to minimize differences in generated
// code.
bool IsShiftedCompressible =
- isInt<6>(ShiftedVal) && !STI.hasFeature(RISCV::TuneLUIADDIFusion);
+ isInt<6>(ShiftedVal) && !STI.hasMacroFusion(RISCV::LUIADDI);
RISCVMatInt::InstSeq TmpSeq;
generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index be93d5933d3329e..8c7f5b4bb91e891 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -34,6 +34,7 @@ include "GISel/RISCVRegisterBanks.td"
// RISC-V Scheduling Models
//===----------------------------------------------------------------------===//
+include "RISCVMacroFusion.td"
include "RISCVSchedRocket.td"
include "RISCVSchedSiFive7.td"
include "RISCVSchedSyntacoreSCR1.td"
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index d6f988ede7f5bf9..3795b512dba1263 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -956,10 +956,6 @@ def TuneDLenFactor2
: SubtargetFeature<"dlen-factor-2", "DLenFactor2", "true",
"Vector unit DLEN(data path width) is half of VLEN">;
-def TuneLUIADDIFusion
- : SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion",
- "true", "Enable LUI+ADDI macrofusion">;
-
def TuneNoDefaultUnroll
: SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
"Disable default unroll preference.">;
@@ -978,8 +974,7 @@ def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
TuneShortForwardBranchOpt]>;
def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
- "Ventana-Veyron Series processors",
- [TuneLUIADDIFusion]>;
+ "Ventana-Veyron Series processors">;
// Assume that lock-free native-width atomics are available, even if the target
// and operating system combination w...
[truncated]
|
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
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||
| // ===---------------------------------------------------------------------===// | ||
| // The following definitions describe the macro fusion predicators. | ||
|
|
There was a problem hiding this comment.
If we had a file MacroFusionUtils which contained same helper functions like checkIsVRegOperaned, would the same code written in C++ be much longer?
There was a problem hiding this comment.
The MacroFusionUtils can be useful to simplify TableGen-generated code. It's a good idea, I will try to implement this later!
mgudim
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| @@ -0,0 +1,208 @@ | |||
| //===--- MacroFusionPredicatorEmitter.cpp - Generator for MacroFusion ----===// | |||
There was a problem hiding this comment.
I wonder if we could use MIR Patterns (https://llvm.org/docs/GlobalISel/MIRPatterns.html) to identify fusions
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Actually my first version of implementation (unfinished) is like this way:
// def fusion1: MacroFusionPat<(FirstInst GPR:$r), (SecondInst GPR:$r)>;
// def fusion2: MacroFusionPat<(FirstInst), (SecondInst GPR:$r)>;
// def fusion3: MacroFusionPat<(FirstInst GPR:$r), (SecondInst)>;
// def fusion4: MacroFusionPat<(FirstInst), (SecondInst)>;
def fusion5: MacroFusionPat<(FirstInst GPR:$r, imm:$imm), (SecondInst _, imm:$imm)>;
We define the predicates of first/second and tied register via dag expressions. But there are some reasons why I gave it up:
- It's hard to write fusion with multiple opcodes (for example,
lui+addi/addiw), we need two definitions (lui+addiandlui+addiw). We can implement it like what we have inTargetSchedule.td, akainstrsandinstregex. But it adds too much complexities to the implementation. - We already have
TargetInstrPredicate.tdto define predicates in SchedModel, which is expressive enough I think.
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Nov 15, 2023
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Doc: https://xiangshan-doc.readthedocs.io/zh-cn/latest/frontend/decode/ This PR is to show the usage of TableGen-based macro fusions. Some instrcution pairs can be folded into one MacroFusion definition but I leave them standalone to show the different ways to define a macro fusion. This PR is stacked on llvm#72219, llvm#72222, llvm#72223, llvm#72224, llvm#72227
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Sorry for bothering, can we merge this into llvm 18 so that we will have a released baseline that supports TableGen-based macro fusion? |
topperc
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Jan 25, 2024
| : SimpleFusion<"auipc-addi-fusion", "HasAUIPCADDIFusion", | ||
| "Enable AUIPC+ADDI macrofusion", | ||
| CheckOpcode<[AUIPC]>, | ||
| CheckOpcode<[ADDI, ADDIW]>>; |
| @@ -1,210 +0,0 @@ | |||
| //===- RISCVMacroFusion.cpp - RISC-V Macro Fusion -------------------------===// | |||
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Do I need to migrate all my downstream macrofusions to tblgen now?
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No, you don't need to.
You can keep this file and override getMacroFusions() in RISCVSubtarget:
std::vector<MacroFusionPredTy> getMacroFusions() const override {
std::vector<MacroFusionPredTy> Fusions =
RISCVGenSubtargetInfo::getMacroFusions();
Fusions.push_back(shouldScheduleAdjacent);
return Fusions;
}shouldScheduleAdjacent is the predicator for your downstream macrofusions.
We convert existed macro fusions to TableGen. Bacause `Fusion` depend on `Instruction` definitions which is defined below `RISCVFeatures.td`, so we recommend user to add fusion features when defining new processor.
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We convert existed macro fusions to TableGen. Bacause `Fusion` depend on `Instruction` definitions which is defined below `RISCVFeatures.td`, so we recommend user to add fusion features when defining new processor. (cherry picked from commit 3fdb431)
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We convert existed macro fusions to TableGen. Bacause `Fusion` depend on `Instruction` definitions which is defined below `RISCVFeatures.td`, so we recommend user to add fusion features when defining new processor. (cherry picked from commit 3fdb431)
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Doc: https://xiangshan-doc.readthedocs.io/zh-cn/latest/frontend/decode/ This PR is to show the usage of TableGen-based macro fusions. Some instrcution pairs can be folded into one MacroFusion definition but I leave them standalone to show the different ways to define a macro fusion. This PR is stacked on llvm#72219, llvm#72222, llvm#72223, llvm#72224, llvm#72227
tstellar
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Feb 14, 2024
We convert existed macro fusions to TableGen. Bacause `Fusion` depend on `Instruction` definitions which is defined below `RISCVFeatures.td`, so we recommend user to add fusion features when defining new processor. (cherry picked from commit 3fdb431)
tstellar
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Feb 14, 2024
We convert existed macro fusions to TableGen. Bacause `Fusion` depend on `Instruction` definitions which is defined below `RISCVFeatures.td`, so we recommend user to add fusion features when defining new processor. (cherry picked from commit 3fdb431)
tstellar
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Feb 14, 2024
We convert existed macro fusions to TableGen. Bacause `Fusion` depend on `Instruction` definitions which is defined below `RISCVFeatures.td`, so we recommend user to add fusion features when defining new processor. (cherry picked from commit 3fdb431)
tstellar
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Feb 14, 2024
We convert existed macro fusions to TableGen. Bacause `Fusion` depend on `Instruction` definitions which is defined below `RISCVFeatures.td`, so we recommend user to add fusion features when defining new processor. (cherry picked from commit 3fdb431)
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We convert existed macro fusions to TableGen.
Bacause
Fusiondepend onInstructiondefinitions which is definedbelow
RISCVFeatures.td, so we recommend user to add fusion featureswhen defining new processor.