reland [InlineAsm] wrap ConstraintCode in enum class NFC #66264

nickdesaulniers · 2023-09-13T17:49:17Z

reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66003)

This reverts commit ee643b7.

Fix up build failures in targets I missed in #66003

Kept as 3 commits for reviewers to see better what's changed. Will squash when
merging.

reland [InlineAsm] wrap ConstraintCode in enum class NFC ([InlineAsm] wrap ConstraintCode in enum class NFC #66003)
fix all the targets I missed in [InlineAsm] wrap ConstraintCode in enum class NFC #66003
fix off by one found by llvm/test/CodeGen/SystemZ/inline-asm-addr.ll

This reverts commit ee643b7. Fix up build failures I missed in llvm#66003

llvmbot · 2023-09-13T17:50:15Z

@llvm/pr-subscribers-backend-aarch64

@llvm/pr-subscribers-backend-risc-v

Changes

reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66003)

This reverts commit ee643b7.

Fix up build failures in targets I missed in #66003

Kept as 3 commits for reviewers to see better what's changed. Will squash when
merging.

reland [InlineAsm] wrap ConstraintCode in enum class NFC ([InlineAsm] wrap ConstraintCode in enum class NFC #66003)
fix all the targets I missed in [InlineAsm] wrap ConstraintCode in enum class NFC #66003
fix off by one found by llvm/test/CodeGen/SystemZ/inline-asm-addr.ll

--

Patch is 69.25 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66264.diff

50 Files Affected:

(modified) llvm/include/llvm/CodeGen/SelectionDAGISel.h (+4-3)
(modified) llvm/include/llvm/CodeGen/TargetLowering.h (+7-6)
(modified) llvm/include/llvm/IR/InlineAsm.h (+78-78)
(modified) llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp (+3-3)
(modified) llvm/lib/CodeGen/MachineInstr.cpp (+1-1)
(modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (+6-6)
(modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (+2-1)
(modified) llvm/lib/CodeGen/TargetInstrInfo.cpp (+1-1)
(modified) llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (+6-5)
(modified) llvm/lib/Target/AArch64/AArch64ISelLowering.h (+3-2)
(modified) llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp (+15-15)
(modified) llvm/lib/Target/ARM/ARMISelLowering.h (+10-10)
(modified) llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp (+6-4)
(modified) llvm/lib/Target/AVR/AVRISelLowering.cpp (+2-2)
(modified) llvm/lib/Target/AVR/AVRISelLowering.h (+2-1)
(modified) llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp (+5-4)
(modified) llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp (+5-3)
(modified) llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (+6-7)
(modified) llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h (+1-1)
(modified) llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp (+5-3)
(modified) llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp (+6-5)
(modified) llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h (+2-1)
(modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (+5-5)
(modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.h (+2-1)
(modified) llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp (+7-5)
(modified) llvm/lib/Target/M68k/M68kISelLowering.cpp (+5-4)
(modified) llvm/lib/Target/M68k/M68kISelLowering.h (+2-1)
(modified) llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp (+6-5)
(modified) llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp (+6-6)
(modified) llvm/lib/Target/Mips/MipsISelDAGToDAG.h (+1-1)
(modified) llvm/lib/Target/Mips/MipsISelLowering.h (+4-4)
(modified) llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (+7-7)
(modified) llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h (+1-1)
(modified) llvm/lib/Target/Mips/MipsSERegisterInfo.cpp (+1-1)
(modified) llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp (+3-2)
(modified) llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h (+4-2)
(modified) llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (+9-8)
(modified) llvm/lib/Target/PowerPC/PPCISelLowering.h (+5-5)
(modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+5-4)
(modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h (+2-1)
(modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+2-2)
(modified) llvm/lib/Target/RISCV/RISCVISelLowering.h (+2-1)
(modified) llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp (+9-10)
(modified) llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (+17-17)
(modified) llvm/lib/Target/SystemZ/SystemZISelLowering.h (+11-10)
(modified) llvm/lib/Target/VE/VEISelDAGToDAG.cpp (+6-7)
(modified) llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp (+5-3)
(modified) llvm/lib/Target/X86/X86ISelDAGToDAG.cpp (+9-9)
(modified) llvm/lib/Target/X86/X86ISelLowering.h (+2-2)
(modified) llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp (+6-5)

<pre>
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 557c6ef03d96b98..0179cf8a1f5925c 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -89,9 +89,10 @@ class SelectionDAGISel : public MachineFunctionPass {
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.

virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,

                                       unsigned ConstraintID,

                                       std::vector&amp;lt;SDValue&amp;gt; &amp;amp;OutOps) {

virtual bool
SelectInlineAsmMemoryOperand(const SDValue &Op,

                          InlineAsm::ConstraintCode ConstraintID,

                          std::vector&amp;lt;SDValue&amp;gt; &amp;amp;OutOps) {

return true;
}

diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 12b280d5b1a0bcd..f4feab495932294 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4833,16 +4833,17 @@ class TargetLowering : public TargetLoweringBase {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const;

virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {

virtual InlineAsm::ConstraintCode
getInlineAsmMemConstraint(StringRef ConstraintCode) const {
if (ConstraintCode == "m")

```
 return InlineAsm::Constraint_m;
```

```
 return InlineAsm::ConstraintCode::m;
```
if (ConstraintCode == "o")

```
 return InlineAsm::Constraint_o;
```

```
 return InlineAsm::ConstraintCode::o;
```
if (ConstraintCode == "X")

```
 return InlineAsm::Constraint_X;
```

```
 return InlineAsm::ConstraintCode::X;
```
if (ConstraintCode == "p")

```
 return InlineAsm::Constraint_p;
```
return InlineAsm::Constraint_Unknown;

```
 return InlineAsm::ConstraintCode::p;
```
return InlineAsm::ConstraintCode::Unknown;
}

/// Try to replace an X constraint, which matches anything, with another that
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index 8a129337f59266d..36ff7deb6864e2f 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -217,48 +217,6 @@ class InlineAsm final : public Value {
Extra_MayLoad = 8,
Extra_MayStore = 16,
Extra_IsConvergent = 32,

// Memory constraint codes.
// These could be tablegenerated but there's little need to do that since
// there's plenty of space in the encoding to support the union of all
// constraint codes for all targets.
// Addresses are included here as they need to be treated the same by the
// backend, the only difference is that they are not used to actaully
// access memory by the instruction.
// TODO: convert to enum?
Constraint_Unknown = 0,
Constraint_es,
Constraint_i,
Constraint_k,
Constraint_m,
Constraint_o,
Constraint_v,
Constraint_A,
Constraint_Q,
Constraint_R,
Constraint_S,
Constraint_T,
Constraint_Um,
Constraint_Un,
Constraint_Uq,
Constraint_Us,
Constraint_Ut,
Constraint_Uv,
Constraint_Uy,
Constraint_X,
Constraint_Z,
Constraint_ZB,
Constraint_ZC,
Constraint_Zy,
// Address constraints
Constraint_p,
Constraint_ZQ,
Constraint_ZR,
Constraint_ZS,
Constraint_ZT,
Constraints_Max = Constraint_ZT,
};

// Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -274,6 +232,46 @@ class InlineAsm final : public Value {
Func = 7, // Address operand of function call
};

// Memory constraint codes.
// Addresses are included here as they need to be treated the same by the
// backend, the only difference is that they are not used to actaully
// access memory by the instruction.
enum class ConstraintCode : uint32_t {
Unknown = 0,
es,
i,
k,
m,
o,
v,
A,
Q,
R,
S,
T,
Um,
Un,
Uq,
Us,
Ut,
Uv,
Uy,
X,
Z,
ZB,
ZC,
Zy,
// Address constraints
p,
ZQ,
ZR,
ZS,
ZT,
Max = ZT,
};
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
//
@@ -375,11 +373,14 @@ class InlineAsm final : public Value {
return true;
}

// TODO: convert to enum?
unsigned getMemoryConstraintID() const {

ConstraintCode getMemoryConstraintID() const {
assert((isMemKind() || isFuncKind()) &&
"Not expected mem or function flag!");

```
 return getData();
```

```
 uint32_t D = getData();
```

 assert(D &amp;lt;= static_cast&amp;lt;uint32_t&amp;gt;(ConstraintCode::Max) &amp;amp;&amp;amp;

        D &amp;gt;= static_cast&amp;lt;uint32_t&amp;gt;(ConstraintCode::Unknown) &amp;amp;&amp;amp;

        &amp;quot;unexpected value for memory constraint&amp;quot;);

```
 return static_cast&amp;lt;ConstraintCode&amp;gt;(D);
```
}

/// setMatchingOp - Augment an existing flag with information indicating
@@ -403,12 +404,11 @@ class InlineAsm final : public Value {

/// setMemConstraint - Augment an existing flag with the constraint code for
/// a memory constraint.

void setMemConstraint(unsigned Constraint) {

void setMemConstraint(ConstraintCode C) {
assert((isMemKind() || isFuncKind()) &&
"Flag is not a memory or function constraint!");

 assert(Constraint &amp;lt;= Constraints_Max &amp;amp;&amp;amp; &amp;quot;Unknown constraint ID&amp;quot;);
 assert(getData() == 0 &amp;amp;&amp;amp; &amp;quot;Mem constraint already set&amp;quot;);

```
 setData(Constraint);
```

```
 setData(static_cast&amp;lt;uint32_t&amp;gt;(C));
```
}
/// clearMemConstraint - Similar to setMemConstraint(0), but without the
/// assertion checking that the constraint has not been set previously.
@@ -443,63 +443,63 @@ class InlineAsm final : public Value {
return Result;
}

static StringRef getMemConstraintName(unsigned Constraint) {
switch (Constraint) {
case InlineAsm::Constraint_es:

static StringRef getMemConstraintName(ConstraintCode C) {
switch (C) {
case ConstraintCode::es:
return "es";

case InlineAsm::Constraint_i:

case ConstraintCode::i:
return "i";

case InlineAsm::Constraint_k:

case ConstraintCode::k:
return "k";

case InlineAsm::Constraint_m:

case ConstraintCode::m:
return "m";

case InlineAsm::Constraint_o:

case ConstraintCode::o:
return "o";

case InlineAsm::Constraint_v:

case ConstraintCode::v:
return "v";

case InlineAsm::Constraint_A:

case ConstraintCode::A:
return "A";

case InlineAsm::Constraint_Q:

case ConstraintCode::Q:
return "Q";

case InlineAsm::Constraint_R:

case ConstraintCode::R:
return "R";

case InlineAsm::Constraint_S:

case ConstraintCode::S:
return "S";

case InlineAsm::Constraint_T:

case ConstraintCode::T:
return "T";

case InlineAsm::Constraint_Um:

case ConstraintCode::Um:
return "Um";

case InlineAsm::Constraint_Un:

case ConstraintCode::Un:
return "Un";

case InlineAsm::Constraint_Uq:

case ConstraintCode::Uq:
return "Uq";

case InlineAsm::Constraint_Us:

case ConstraintCode::Us:
return "Us";

case InlineAsm::Constraint_Ut:

case ConstraintCode::Ut:
return "Ut";

case InlineAsm::Constraint_Uv:

case ConstraintCode::Uv:
return "Uv";

case InlineAsm::Constraint_Uy:

case ConstraintCode::Uy:
return "Uy";

case InlineAsm::Constraint_X:

case ConstraintCode::X:
return "X";

case InlineAsm::Constraint_Z:

case ConstraintCode::Z:
return "Z";

case InlineAsm::Constraint_ZB:

case ConstraintCode::ZB:
return "ZB";

case InlineAsm::Constraint_ZC:

case ConstraintCode::ZC:
return "ZC";

case InlineAsm::Constraint_Zy:

case ConstraintCode::Zy:
return "Zy";

case InlineAsm::Constraint_p:

case ConstraintCode::p:
return "p";

case InlineAsm::Constraint_ZQ:

case ConstraintCode::ZQ:
return "ZQ";

case InlineAsm::Constraint_ZR:

case ConstraintCode::ZR:
return "ZR";

case InlineAsm::Constraint_ZS:

case ConstraintCode::ZS:
return "ZS";

case InlineAsm::Constraint_ZT:

case ConstraintCode::ZT:
return "ZT";
default:
llvm_unreachable("Unknown memory constraint");
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 9944ba15997687a..00dba57fcb80227 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {

```
   unsigned ConstraintID =
```

   const InlineAsm::ConstraintCode ConstraintID =
       TLI-&amp;gt;getInlineAsmMemConstraint(OpInfo.ConstraintCode);

   assert(ConstraintID != InlineAsm::Constraint_Unknown &amp;amp;&amp;amp;

   assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &amp;amp;&amp;amp;
          &amp;quot;Failed to convert memory constraint code to constraint id.&amp;quot;);

   // Add information to the INLINEASM instruction to know about this

@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(

     assert(OpInfo.isIndirect &amp;amp;&amp;amp; &amp;quot;Operand must be indirect to be a mem!&amp;quot;);

```
   unsigned ConstraintID =
```

   const InlineAsm::ConstraintCode ConstraintID =
       TLI-&amp;gt;getInlineAsmMemConstraint(OpInfo.ConstraintCode);
   InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
   OpFlags.setMemConstraint(ConstraintID);

diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 8cc3391e0d96a3d..d8467e2af8786ec 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
}

   if (F.isMemKind()) {

   const unsigned MCID = F.getMemoryConstraintID();

   const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
   OS &amp;lt;&amp;lt; &amp;quot;:&amp;quot; &amp;lt;&amp;lt; InlineAsm::getMemConstraintName(MCID);
 }

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 738dd10633db6a5..720fc4944161225 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {

```
   unsigned ConstraintID =
```

   const InlineAsm::ConstraintCode ConstraintID =
       TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);

   assert(ConstraintID != InlineAsm::Constraint_Unknown &amp;amp;&amp;amp;

   assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &amp;amp;&amp;amp;
          &amp;quot;Failed to convert memory constraint code to constraint id.&amp;quot;);

   // Add information to the INLINEASM node to know about this output.

@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
TLI.getPointerTy(DAG.getDataLayout()) &&
"Memory operands expect pointer values");

```
   unsigned ConstraintID =
```

   const InlineAsm::ConstraintCode ConstraintID =
       TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);

   assert(ConstraintID != InlineAsm::Constraint_Unknown &amp;amp;&amp;amp;

   assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &amp;amp;&amp;amp;
          &amp;quot;Failed to convert memory constraint code to constraint id.&amp;quot;);

   // Add information to the INLINEASM node to know about this input.

@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
}

   if (OpInfo.ConstraintType == TargetLowering::C_Address) {

```
   unsigned ConstraintID =
```

   const InlineAsm::ConstraintCode ConstraintID =
       TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);

   assert(ConstraintID != InlineAsm::Constraint_Unknown &amp;amp;&amp;amp;

   assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &amp;amp;&amp;amp;
          &amp;quot;Failed to convert memory constraint code to constraint id.&amp;quot;);

   InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a7873241df62e52..91b9d77eed70596 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2101,7 +2101,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,

   // Otherwise, this is a memory operand.  Ask the target to select it.
   std::vector&amp;lt;SDValue&amp;gt; SelOps;

 unsigned ConstraintID = Flags.getMemoryConstraintID();

 const InlineAsm::ConstraintCode ConstraintID =

     Flags.getMemoryConstraintID();
 if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
   report_fatal_error(&amp;quot;Could not match memory address.  Inline asm&amp;quot;
                      &amp;quot; failure!&amp;quot;);

diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 686044ea572ac0d..bf1605f06bd88d6 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
}

if (F.isMemKind()) {

const unsigned MCID = F.getMemoryConstraintID();

InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}

diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 60a155a86667e89..16ab662ca34aa4f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -62,7 +62,7 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,

                               unsigned ConstraintID,

                               InlineAsm::ConstraintCode ConstraintID,
                               std::vector&amp;lt;SDValue&amp;gt; &amp;amp;OutOps) override;

template <signed Low, signed High, signed Scale>
@@ -533,13 +533,14 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
#endif

bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(

const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {

const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");

case InlineAsm::Constraint_m:
case InlineAsm::Constraint_o:
case InlineAsm::Constraint_Q:

case InlineAsm::ConstraintCode::m:
case InlineAsm::ConstraintCode::o:
case InlineAsm::ConstraintCode::Q:
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 67c344318e0d3ec..f2696b6b97593a1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1169,9 +1169,10 @@ class AArch64TargetLowering : public TargetLowering {
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;

unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {

InlineAsm::ConstraintCode
getInlineAsmMemConstraint(StringRef ConstraintCode) const overri...

rnk

Looks good, I spot checked the Mips and SystemZ issues I saw locally. I think some stuff just got lost in your rebase attempt. I see the buildkite checks on Linux passed on this PR and the previous one.

nickdesaulniers · 2023-09-13T20:05:39Z

Looks good, I spot checked the Mips and SystemZ issues I saw locally. I think some stuff just got lost in your rebase attempt. I see the buildkite checks on Linux passed on this PR and the previous one.

Thanks, looks like 142c89c is the culprit of that unittest failure on windows.

danilaml · 2023-09-14T12:15:56Z

llvm/include/llvm/IR/InlineAsm.h

-      return getData();
+      uint32_t D = getData();
+      assert(D <= static_cast<uint32_t>(ConstraintCode::Max) &&
+             D >= static_cast<uint32_t>(ConstraintCode::Unknown) &&


Note that this triggers type-limits warning (if it's enabled) on GCC 7 and 8.

error: comparison of unsigned expression >= 0 is always true

Don't know if there is a nice way to silence it and if we want to keep this check.

Thanks for the report.

I'm about to delete this newly added code in #66297.

reland [InlineAsm] wrap ConstraintCode in enum class NFC (llvm#66003) This reverts commit ee643b7. Fix up build failures in targets I missed in llvm#66003 Kept as 3 commits for reviewers to see better what's changed. Will squash when merging. - reland [InlineAsm] wrap ConstraintCode in enum class NFC (llvm#66003) - fix all the targets I missed in llvm#66003 - fix off by one found by llvm/test/CodeGen/SystemZ/inline-asm-addr.ll

nickdesaulniers requested review from a team as code owners September 13, 2023 17:49

nickdesaulniers added 3 commits September 13, 2023 10:49

reland [InlineAsm] wrap ConstraintCode in enum class NFC (llvm#66003)

ab68742

This reverts commit ee643b7. Fix up build failures I missed in llvm#66003

fix all the targets I missed in llvm#66003

0662f8d

fix off by one found by llvm/test/CodeGen/SystemZ/inline-asm-addr.ll

fd0fa2b

llvmbot added backend:ARM backend:AArch64 backend:MSP430 backend:RISC-V backend:Sparc backend:WebAssembly backend:X86 llvm:globalisel backend:m68k backend:loongarch llvm:SelectionDAG SelectionDAGISel as well llvm:ir labels Sep 13, 2023

nickdesaulniers force-pushed the asm_reland branch from 0ab9f2a to fd0fa2b Compare September 13, 2023 17:49

nickdesaulniers requested a review from jyknight September 13, 2023 17:50

nickdesaulniers requested a review from rnk September 13, 2023 17:50

nickdesaulniers mentioned this pull request Sep 13, 2023

[InlineAsm] wrap ConstraintCode in enum class NFC #66003

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nickdesaulniers changed the title ~~asm reland~~ reland [InlineAsm] wrap ConstraintCode in enum class NFC Sep 13, 2023

rnk approved these changes Sep 13, 2023

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nickdesaulniers merged commit 86735a4 into llvm:main Sep 13, 2023
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nickdesaulniers deleted the asm_reland branch September 13, 2023 20:31

danilaml reviewed Sep 14, 2023

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reland [InlineAsm] wrap ConstraintCode in enum class NFC #66264

reland [InlineAsm] wrap ConstraintCode in enum class NFC #66264

nickdesaulniers commented Sep 13, 2023

llvmbot commented Sep 13, 2023 •

edited

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nickdesaulniers commented Sep 13, 2023

danilaml Sep 14, 2023

nickdesaulniers Sep 14, 2023

reland [InlineAsm] wrap ConstraintCode in enum class NFC #66264

reland [InlineAsm] wrap ConstraintCode in enum class NFC #66264

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nickdesaulniers commented Sep 13, 2023

llvmbot commented Sep 13, 2023 • edited

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nickdesaulniers commented Sep 13, 2023

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llvmbot commented Sep 13, 2023 •

edited