[InlineAsm] wrap ConstraintCode in enum class NFC #66003
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nickdesaulniers
requested review from
jyknight,
isanbard,
bwendling and
qcolombet
llvmbot
added
backend:ARM
backend:AArch64
backend:RISC-V
backend:X86
llvm:globalisel
backend:m68k
llvm:SelectionDAG
|
@llvm/pr-subscribers-backend-risc-v ChangesSimilar to Fix the TODOs added in -- Patch is 34.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66003.diff 25 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 557c6ef03d96b98..d3907865a659121 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -89,9 +89,10 @@ class SelectionDAGISel : public MachineFunctionPass {
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) {
+ virtual bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
return true;
}
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 12b280d5b1a0bcd..f4feab495932294 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4833,16 +4833,17 @@ class TargetLowering : public TargetLoweringBase {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const;
- virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+ virtual InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const {
if (ConstraintCode == "m")
- return InlineAsm::Constraint_m;
+ return InlineAsm::ConstraintCode::m;
if (ConstraintCode == "o")
- return InlineAsm::Constraint_o;
+ return InlineAsm::ConstraintCode::o;
if (ConstraintCode == "X")
- return InlineAsm::Constraint_X;
+ return InlineAsm::ConstraintCode::X;
if (ConstraintCode == "p")
- return InlineAsm::Constraint_p;
- return InlineAsm::Constraint_Unknown;
+ return InlineAsm::ConstraintCode::p;
+ return InlineAsm::ConstraintCode::Unknown;
}
/// Try to replace an X constraint, which matches anything, with another that
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index f73666fa8dc08e7..a4032ce7abde331 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -217,48 +217,6 @@ class InlineAsm final : public Value {
Extra_MayLoad = 8,
Extra_MayStore = 16,
Extra_IsConvergent = 32,
-
- // Memory constraint codes.
- // These could be tablegenerated but there's little need to do that since
- // there's plenty of space in the encoding to support the union of all
- // constraint codes for all targets.
- // Addresses are included here as they need to be treated the same by the
- // backend, the only difference is that they are not used to actaully
- // access memory by the instruction.
- // TODO: convert to enum?
- Constraint_Unknown = 0,
- Constraint_es,
- Constraint_i,
- Constraint_k,
- Constraint_m,
- Constraint_o,
- Constraint_v,
- Constraint_A,
- Constraint_Q,
- Constraint_R,
- Constraint_S,
- Constraint_T,
- Constraint_Um,
- Constraint_Un,
- Constraint_Uq,
- Constraint_Us,
- Constraint_Ut,
- Constraint_Uv,
- Constraint_Uy,
- Constraint_X,
- Constraint_Z,
- Constraint_ZB,
- Constraint_ZC,
- Constraint_Zy,
-
- // Address constraints
- Constraint_p,
- Constraint_ZQ,
- Constraint_ZR,
- Constraint_ZS,
- Constraint_ZT,
-
- Constraints_Max = Constraint_ZT,
};
// Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -274,6 +232,46 @@ class InlineAsm final : public Value {
Func = 7, // Address operand of function call
};
+ // Memory constraint codes.
+ // Addresses are included here as they need to be treated the same by the
+ // backend, the only difference is that they are not used to actaully
+ // access memory by the instruction.
+ enum class ConstraintCode : uint32_t {
+ Unknown = 0,
+ es,
+ i,
+ k,
+ m,
+ o,
+ v,
+ A,
+ Q,
+ R,
+ S,
+ T,
+ Um,
+ Un,
+ Uq,
+ Us,
+ Ut,
+ Uv,
+ Uy,
+ X,
+ Z,
+ ZB,
+ ZC,
+ Zy,
+
+ // Address constraints
+ p,
+ ZQ,
+ ZR,
+ ZS,
+ ZT,
+
+ Max = ZT,
+ };
+
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
//
@@ -375,11 +373,14 @@ class InlineAsm final : public Value {
return true;
}
- // TODO: convert to enum?
- unsigned getMemoryConstraintID() const {
+ ConstraintCode getMemoryConstraintID() const {
assert((isMemKind() || isFuncKind()) &&
"Not expected mem or function flag!");
- return getData();
+ uint32_t D = getData();
+ assert(D < static_cast(ConstraintCode::Max) &&
+ D >= static_cast(ConstraintCode::Unknown) &&
+ "unexpected value for memory constraint");
+ return static_cast(D);
}
/// setMatchingOp - Augment an existing flag with information indicating
@@ -403,12 +404,11 @@ class InlineAsm final : public Value {
/// setMemConstraint - Augment an existing flag with the constraint code for
/// a memory constraint.
- void setMemConstraint(unsigned Constraint) {
+ void setMemConstraint(ConstraintCode C) {
assert((isMemKind() || isFuncKind()) &&
"Flag is not a memory or function constraint!");
- assert(Constraint <= Constraints_Max && "Unknown constraint ID");
assert(getData() == 0 && "Mem constraint already set");
- setData(Constraint);
+ setData(static_cast(C));
}
/// clearMemConstraint - Similar to setMemConstraint(0), but without the
/// assertion checking that the constraint has not been set previously.
@@ -443,61 +443,61 @@ class InlineAsm final : public Value {
return Result;
}
- static StringRef getMemConstraintName(unsigned Constraint) {
- switch (Constraint) {
- case InlineAsm::Constraint_es:
+ static StringRef getMemConstraintName(const ConstraintCode C) {
+ switch (C) {
+ case ConstraintCode::es:
return "es";
- case InlineAsm::Constraint_i:
+ case ConstraintCode::i:
return "i";
- case InlineAsm::Constraint_k:
+ case ConstraintCode::k:
return "k";
- case InlineAsm::Constraint_m:
+ case ConstraintCode::m:
return "m";
- case InlineAsm::Constraint_o:
+ case ConstraintCode::o:
return "o";
- case InlineAsm::Constraint_v:
+ case ConstraintCode::v:
return "v";
- case InlineAsm::Constraint_Q:
+ case ConstraintCode::Q:
return "Q";
- case InlineAsm::Constraint_R:
+ case ConstraintCode::R:
return "R";
- case InlineAsm::Constraint_S:
+ case ConstraintCode::S:
return "S";
- case InlineAsm::Constraint_T:
+ case ConstraintCode::T:
return "T";
- case InlineAsm::Constraint_Um:
+ case ConstraintCode::Um:
return "Um";
- case InlineAsm::Constraint_Un:
+ case ConstraintCode::Un:
return "Un";
- case InlineAsm::Constraint_Uq:
+ case ConstraintCode::Uq:
return "Uq";
- case InlineAsm::Constraint_Us:
+ case ConstraintCode::Us:
return "Us";
- case InlineAsm::Constraint_Ut:
+ case ConstraintCode::Ut:
return "Ut";
- case InlineAsm::Constraint_Uv:
+ case ConstraintCode::Uv:
return "Uv";
- case InlineAsm::Constraint_Uy:
+ case ConstraintCode::Uy:
return "Uy";
- case InlineAsm::Constraint_X:
+ case ConstraintCode::X:
return "X";
- case InlineAsm::Constraint_Z:
+ case ConstraintCode::Z:
return "Z";
- case InlineAsm::Constraint_ZB:
+ case ConstraintCode::ZB:
return "ZB";
- case InlineAsm::Constraint_ZC:
+ case ConstraintCode::ZC:
return "ZC";
- case InlineAsm::Constraint_Zy:
+ case ConstraintCode::Zy:
return "Zy";
- case InlineAsm::Constraint_p:
+ case ConstraintCode::p:
return "p";
- case InlineAsm::Constraint_ZQ:
+ case ConstraintCode::ZQ:
return "ZQ";
- case InlineAsm::Constraint_ZR:
+ case ConstraintCode::ZR:
return "ZR";
- case InlineAsm::Constraint_ZS:
+ case ConstraintCode::ZS:
return "ZS";
- case InlineAsm::Constraint_ZT:
+ case ConstraintCode::ZT:
return "ZT";
default:
llvm_unreachable("Unknown memory constraint");
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 9944ba15997687a..00dba57fcb80227 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
OpFlags.setMemConstraint(ConstraintID);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 8cc3391e0d96a3d..d8467e2af8786ec 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 738dd10633db6a5..720fc4944161225 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
TLI.getPointerTy(DAG.getDataLayout()) &&
"Memory operands expect pointer values");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
}
if (OpInfo.ConstraintType == TargetLowering::C_Address) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a7873241df62e52..91b9d77eed70596 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2101,7 +2101,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector &Ops,
// Otherwise, this is a memory operand. Ask the target to select it.
std::vector SelOps;
- unsigned ConstraintID = Flags.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode ConstraintID =
+ Flags.getMemoryConstraintID();
if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
report_fatal_error("Could not match memory address. Inline asm"
" failure!");
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 686044ea572ac0d..bf1605f06bd88d6 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 60a155a86667e89..740995849740fef 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -61,9 +61,10 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
template
bool SelectRDVLImm(SDValue N, SDValue &Imm);
@@ -533,13 +534,14 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
#endif
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 67c344318e0d3ec..f2696b6b97593a1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1169,9 +1169,10 @@ class AArch64TargetLowering : public TargetLowering {
std::vector &Ops,
SelectionDAG &DAG) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
// followed by llvm_unreachable so we'll leave them unimplemented in
// the backend for now.
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 5f4fab0675824fd..9956b1b040b329d 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -331,8 +331,10 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
// Form pairs of consecutive R, S, D, or Q registers.
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
@@ -5864,23 +5866,22 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
return true;
}
-
-bool ARMDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) {
+bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
- case InlineAsm::Constraint_Um:
- case InlineAsm::Constraint_Un:
- case InlineAsm::Constraint_Uq:
- case InlineAsm::Constraint_Us:
- case InlineAsm::Constraint_Ut:
- case InlineAsm::Constraint_Uv:
- case InlineAsm::Constraint_Uy:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::ConstraintCode::Um:
+ case InlineAsm::ConstraintCode::Un:
+ case InlineAsm::ConstraintCode::Uq:
+ case InlineAsm::ConstraintCode::Us:
+ case InlineAsm::ConstraintCod...
|
|
@llvm/pr-subscribers-backend-aarch64 ChangesSimilar to Fix the TODOs added in -- Patch is 34.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66003.diff 25 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 557c6ef03d96b98..d3907865a659121 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -89,9 +89,10 @@ class SelectionDAGISel : public MachineFunctionPass {
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) {
+ virtual bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
return true;
}
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 12b280d5b1a0bcd..f4feab495932294 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4833,16 +4833,17 @@ class TargetLowering : public TargetLoweringBase {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const;
- virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+ virtual InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const {
if (ConstraintCode == "m")
- return InlineAsm::Constraint_m;
+ return InlineAsm::ConstraintCode::m;
if (ConstraintCode == "o")
- return InlineAsm::Constraint_o;
+ return InlineAsm::ConstraintCode::o;
if (ConstraintCode == "X")
- return InlineAsm::Constraint_X;
+ return InlineAsm::ConstraintCode::X;
if (ConstraintCode == "p")
- return InlineAsm::Constraint_p;
- return InlineAsm::Constraint_Unknown;
+ return InlineAsm::ConstraintCode::p;
+ return InlineAsm::ConstraintCode::Unknown;
}
/// Try to replace an X constraint, which matches anything, with another that
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index f73666fa8dc08e7..a4032ce7abde331 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -217,48 +217,6 @@ class InlineAsm final : public Value {
Extra_MayLoad = 8,
Extra_MayStore = 16,
Extra_IsConvergent = 32,
-
- // Memory constraint codes.
- // These could be tablegenerated but there's little need to do that since
- // there's plenty of space in the encoding to support the union of all
- // constraint codes for all targets.
- // Addresses are included here as they need to be treated the same by the
- // backend, the only difference is that they are not used to actaully
- // access memory by the instruction.
- // TODO: convert to enum?
- Constraint_Unknown = 0,
- Constraint_es,
- Constraint_i,
- Constraint_k,
- Constraint_m,
- Constraint_o,
- Constraint_v,
- Constraint_A,
- Constraint_Q,
- Constraint_R,
- Constraint_S,
- Constraint_T,
- Constraint_Um,
- Constraint_Un,
- Constraint_Uq,
- Constraint_Us,
- Constraint_Ut,
- Constraint_Uv,
- Constraint_Uy,
- Constraint_X,
- Constraint_Z,
- Constraint_ZB,
- Constraint_ZC,
- Constraint_Zy,
-
- // Address constraints
- Constraint_p,
- Constraint_ZQ,
- Constraint_ZR,
- Constraint_ZS,
- Constraint_ZT,
-
- Constraints_Max = Constraint_ZT,
};
// Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -274,6 +232,46 @@ class InlineAsm final : public Value {
Func = 7, // Address operand of function call
};
+ // Memory constraint codes.
+ // Addresses are included here as they need to be treated the same by the
+ // backend, the only difference is that they are not used to actaully
+ // access memory by the instruction.
+ enum class ConstraintCode : uint32_t {
+ Unknown = 0,
+ es,
+ i,
+ k,
+ m,
+ o,
+ v,
+ A,
+ Q,
+ R,
+ S,
+ T,
+ Um,
+ Un,
+ Uq,
+ Us,
+ Ut,
+ Uv,
+ Uy,
+ X,
+ Z,
+ ZB,
+ ZC,
+ Zy,
+
+ // Address constraints
+ p,
+ ZQ,
+ ZR,
+ ZS,
+ ZT,
+
+ Max = ZT,
+ };
+
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
//
@@ -375,11 +373,14 @@ class InlineAsm final : public Value {
return true;
}
- // TODO: convert to enum?
- unsigned getMemoryConstraintID() const {
+ ConstraintCode getMemoryConstraintID() const {
assert((isMemKind() || isFuncKind()) &&
"Not expected mem or function flag!");
- return getData();
+ uint32_t D = getData();
+ assert(D < static_cast(ConstraintCode::Max) &&
+ D >= static_cast(ConstraintCode::Unknown) &&
+ "unexpected value for memory constraint");
+ return static_cast(D);
}
/// setMatchingOp - Augment an existing flag with information indicating
@@ -403,12 +404,11 @@ class InlineAsm final : public Value {
/// setMemConstraint - Augment an existing flag with the constraint code for
/// a memory constraint.
- void setMemConstraint(unsigned Constraint) {
+ void setMemConstraint(ConstraintCode C) {
assert((isMemKind() || isFuncKind()) &&
"Flag is not a memory or function constraint!");
- assert(Constraint <= Constraints_Max && "Unknown constraint ID");
assert(getData() == 0 && "Mem constraint already set");
- setData(Constraint);
+ setData(static_cast(C));
}
/// clearMemConstraint - Similar to setMemConstraint(0), but without the
/// assertion checking that the constraint has not been set previously.
@@ -443,61 +443,61 @@ class InlineAsm final : public Value {
return Result;
}
- static StringRef getMemConstraintName(unsigned Constraint) {
- switch (Constraint) {
- case InlineAsm::Constraint_es:
+ static StringRef getMemConstraintName(const ConstraintCode C) {
+ switch (C) {
+ case ConstraintCode::es:
return "es";
- case InlineAsm::Constraint_i:
+ case ConstraintCode::i:
return "i";
- case InlineAsm::Constraint_k:
+ case ConstraintCode::k:
return "k";
- case InlineAsm::Constraint_m:
+ case ConstraintCode::m:
return "m";
- case InlineAsm::Constraint_o:
+ case ConstraintCode::o:
return "o";
- case InlineAsm::Constraint_v:
+ case ConstraintCode::v:
return "v";
- case InlineAsm::Constraint_Q:
+ case ConstraintCode::Q:
return "Q";
- case InlineAsm::Constraint_R:
+ case ConstraintCode::R:
return "R";
- case InlineAsm::Constraint_S:
+ case ConstraintCode::S:
return "S";
- case InlineAsm::Constraint_T:
+ case ConstraintCode::T:
return "T";
- case InlineAsm::Constraint_Um:
+ case ConstraintCode::Um:
return "Um";
- case InlineAsm::Constraint_Un:
+ case ConstraintCode::Un:
return "Un";
- case InlineAsm::Constraint_Uq:
+ case ConstraintCode::Uq:
return "Uq";
- case InlineAsm::Constraint_Us:
+ case ConstraintCode::Us:
return "Us";
- case InlineAsm::Constraint_Ut:
+ case ConstraintCode::Ut:
return "Ut";
- case InlineAsm::Constraint_Uv:
+ case ConstraintCode::Uv:
return "Uv";
- case InlineAsm::Constraint_Uy:
+ case ConstraintCode::Uy:
return "Uy";
- case InlineAsm::Constraint_X:
+ case ConstraintCode::X:
return "X";
- case InlineAsm::Constraint_Z:
+ case ConstraintCode::Z:
return "Z";
- case InlineAsm::Constraint_ZB:
+ case ConstraintCode::ZB:
return "ZB";
- case InlineAsm::Constraint_ZC:
+ case ConstraintCode::ZC:
return "ZC";
- case InlineAsm::Constraint_Zy:
+ case ConstraintCode::Zy:
return "Zy";
- case InlineAsm::Constraint_p:
+ case ConstraintCode::p:
return "p";
- case InlineAsm::Constraint_ZQ:
+ case ConstraintCode::ZQ:
return "ZQ";
- case InlineAsm::Constraint_ZR:
+ case ConstraintCode::ZR:
return "ZR";
- case InlineAsm::Constraint_ZS:
+ case ConstraintCode::ZS:
return "ZS";
- case InlineAsm::Constraint_ZT:
+ case ConstraintCode::ZT:
return "ZT";
default:
llvm_unreachable("Unknown memory constraint");
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 9944ba15997687a..00dba57fcb80227 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
OpFlags.setMemConstraint(ConstraintID);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 8cc3391e0d96a3d..d8467e2af8786ec 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 738dd10633db6a5..720fc4944161225 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
TLI.getPointerTy(DAG.getDataLayout()) &&
"Memory operands expect pointer values");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
}
if (OpInfo.ConstraintType == TargetLowering::C_Address) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a7873241df62e52..91b9d77eed70596 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2101,7 +2101,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector &Ops,
// Otherwise, this is a memory operand. Ask the target to select it.
std::vector SelOps;
- unsigned ConstraintID = Flags.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode ConstraintID =
+ Flags.getMemoryConstraintID();
if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
report_fatal_error("Could not match memory address. Inline asm"
" failure!");
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 686044ea572ac0d..bf1605f06bd88d6 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 60a155a86667e89..740995849740fef 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -61,9 +61,10 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
template
bool SelectRDVLImm(SDValue N, SDValue &Imm);
@@ -533,13 +534,14 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
#endif
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 67c344318e0d3ec..f2696b6b97593a1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1169,9 +1169,10 @@ class AArch64TargetLowering : public TargetLowering {
std::vector &Ops,
SelectionDAG &DAG) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
// followed by llvm_unreachable so we'll leave them unimplemented in
// the backend for now.
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 5f4fab0675824fd..9956b1b040b329d 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -331,8 +331,10 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
// Form pairs of consecutive R, S, D, or Q registers.
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
@@ -5864,23 +5866,22 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
return true;
}
-
-bool ARMDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) {
+bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
- case InlineAsm::Constraint_Um:
- case InlineAsm::Constraint_Un:
- case InlineAsm::Constraint_Uq:
- case InlineAsm::Constraint_Us:
- case InlineAsm::Constraint_Ut:
- case InlineAsm::Constraint_Uv:
- case InlineAsm::Constraint_Uy:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::ConstraintCode::Um:
+ case InlineAsm::ConstraintCode::Un:
+ case InlineAsm::ConstraintCode::Uq:
+ case InlineAsm::ConstraintCode::Us:
+ case InlineAsm::ConstraintCod...
|
|
@llvm/pr-subscribers-backend-x86 ChangesSimilar to Fix the TODOs added in -- Patch is 34.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66003.diff 25 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 557c6ef03d96b98..d3907865a659121 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -89,9 +89,10 @@ class SelectionDAGISel : public MachineFunctionPass {
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) {
+ virtual bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
return true;
}
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 12b280d5b1a0bcd..f4feab495932294 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4833,16 +4833,17 @@ class TargetLowering : public TargetLoweringBase {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const;
- virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+ virtual InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const {
if (ConstraintCode == "m")
- return InlineAsm::Constraint_m;
+ return InlineAsm::ConstraintCode::m;
if (ConstraintCode == "o")
- return InlineAsm::Constraint_o;
+ return InlineAsm::ConstraintCode::o;
if (ConstraintCode == "X")
- return InlineAsm::Constraint_X;
+ return InlineAsm::ConstraintCode::X;
if (ConstraintCode == "p")
- return InlineAsm::Constraint_p;
- return InlineAsm::Constraint_Unknown;
+ return InlineAsm::ConstraintCode::p;
+ return InlineAsm::ConstraintCode::Unknown;
}
/// Try to replace an X constraint, which matches anything, with another that
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index f73666fa8dc08e7..a4032ce7abde331 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -217,48 +217,6 @@ class InlineAsm final : public Value {
Extra_MayLoad = 8,
Extra_MayStore = 16,
Extra_IsConvergent = 32,
-
- // Memory constraint codes.
- // These could be tablegenerated but there's little need to do that since
- // there's plenty of space in the encoding to support the union of all
- // constraint codes for all targets.
- // Addresses are included here as they need to be treated the same by the
- // backend, the only difference is that they are not used to actaully
- // access memory by the instruction.
- // TODO: convert to enum?
- Constraint_Unknown = 0,
- Constraint_es,
- Constraint_i,
- Constraint_k,
- Constraint_m,
- Constraint_o,
- Constraint_v,
- Constraint_A,
- Constraint_Q,
- Constraint_R,
- Constraint_S,
- Constraint_T,
- Constraint_Um,
- Constraint_Un,
- Constraint_Uq,
- Constraint_Us,
- Constraint_Ut,
- Constraint_Uv,
- Constraint_Uy,
- Constraint_X,
- Constraint_Z,
- Constraint_ZB,
- Constraint_ZC,
- Constraint_Zy,
-
- // Address constraints
- Constraint_p,
- Constraint_ZQ,
- Constraint_ZR,
- Constraint_ZS,
- Constraint_ZT,
-
- Constraints_Max = Constraint_ZT,
};
// Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -274,6 +232,46 @@ class InlineAsm final : public Value {
Func = 7, // Address operand of function call
};
+ // Memory constraint codes.
+ // Addresses are included here as they need to be treated the same by the
+ // backend, the only difference is that they are not used to actaully
+ // access memory by the instruction.
+ enum class ConstraintCode : uint32_t {
+ Unknown = 0,
+ es,
+ i,
+ k,
+ m,
+ o,
+ v,
+ A,
+ Q,
+ R,
+ S,
+ T,
+ Um,
+ Un,
+ Uq,
+ Us,
+ Ut,
+ Uv,
+ Uy,
+ X,
+ Z,
+ ZB,
+ ZC,
+ Zy,
+
+ // Address constraints
+ p,
+ ZQ,
+ ZR,
+ ZS,
+ ZT,
+
+ Max = ZT,
+ };
+
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
//
@@ -375,11 +373,14 @@ class InlineAsm final : public Value {
return true;
}
- // TODO: convert to enum?
- unsigned getMemoryConstraintID() const {
+ ConstraintCode getMemoryConstraintID() const {
assert((isMemKind() || isFuncKind()) &&
"Not expected mem or function flag!");
- return getData();
+ uint32_t D = getData();
+ assert(D < static_cast(ConstraintCode::Max) &&
+ D >= static_cast(ConstraintCode::Unknown) &&
+ "unexpected value for memory constraint");
+ return static_cast(D);
}
/// setMatchingOp - Augment an existing flag with information indicating
@@ -403,12 +404,11 @@ class InlineAsm final : public Value {
/// setMemConstraint - Augment an existing flag with the constraint code for
/// a memory constraint.
- void setMemConstraint(unsigned Constraint) {
+ void setMemConstraint(ConstraintCode C) {
assert((isMemKind() || isFuncKind()) &&
"Flag is not a memory or function constraint!");
- assert(Constraint <= Constraints_Max && "Unknown constraint ID");
assert(getData() == 0 && "Mem constraint already set");
- setData(Constraint);
+ setData(static_cast(C));
}
/// clearMemConstraint - Similar to setMemConstraint(0), but without the
/// assertion checking that the constraint has not been set previously.
@@ -443,61 +443,61 @@ class InlineAsm final : public Value {
return Result;
}
- static StringRef getMemConstraintName(unsigned Constraint) {
- switch (Constraint) {
- case InlineAsm::Constraint_es:
+ static StringRef getMemConstraintName(const ConstraintCode C) {
+ switch (C) {
+ case ConstraintCode::es:
return "es";
- case InlineAsm::Constraint_i:
+ case ConstraintCode::i:
return "i";
- case InlineAsm::Constraint_k:
+ case ConstraintCode::k:
return "k";
- case InlineAsm::Constraint_m:
+ case ConstraintCode::m:
return "m";
- case InlineAsm::Constraint_o:
+ case ConstraintCode::o:
return "o";
- case InlineAsm::Constraint_v:
+ case ConstraintCode::v:
return "v";
- case InlineAsm::Constraint_Q:
+ case ConstraintCode::Q:
return "Q";
- case InlineAsm::Constraint_R:
+ case ConstraintCode::R:
return "R";
- case InlineAsm::Constraint_S:
+ case ConstraintCode::S:
return "S";
- case InlineAsm::Constraint_T:
+ case ConstraintCode::T:
return "T";
- case InlineAsm::Constraint_Um:
+ case ConstraintCode::Um:
return "Um";
- case InlineAsm::Constraint_Un:
+ case ConstraintCode::Un:
return "Un";
- case InlineAsm::Constraint_Uq:
+ case ConstraintCode::Uq:
return "Uq";
- case InlineAsm::Constraint_Us:
+ case ConstraintCode::Us:
return "Us";
- case InlineAsm::Constraint_Ut:
+ case ConstraintCode::Ut:
return "Ut";
- case InlineAsm::Constraint_Uv:
+ case ConstraintCode::Uv:
return "Uv";
- case InlineAsm::Constraint_Uy:
+ case ConstraintCode::Uy:
return "Uy";
- case InlineAsm::Constraint_X:
+ case ConstraintCode::X:
return "X";
- case InlineAsm::Constraint_Z:
+ case ConstraintCode::Z:
return "Z";
- case InlineAsm::Constraint_ZB:
+ case ConstraintCode::ZB:
return "ZB";
- case InlineAsm::Constraint_ZC:
+ case ConstraintCode::ZC:
return "ZC";
- case InlineAsm::Constraint_Zy:
+ case ConstraintCode::Zy:
return "Zy";
- case InlineAsm::Constraint_p:
+ case ConstraintCode::p:
return "p";
- case InlineAsm::Constraint_ZQ:
+ case ConstraintCode::ZQ:
return "ZQ";
- case InlineAsm::Constraint_ZR:
+ case ConstraintCode::ZR:
return "ZR";
- case InlineAsm::Constraint_ZS:
+ case ConstraintCode::ZS:
return "ZS";
- case InlineAsm::Constraint_ZT:
+ case ConstraintCode::ZT:
return "ZT";
default:
llvm_unreachable("Unknown memory constraint");
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 9944ba15997687a..00dba57fcb80227 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
OpFlags.setMemConstraint(ConstraintID);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 8cc3391e0d96a3d..d8467e2af8786ec 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 738dd10633db6a5..720fc4944161225 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
TLI.getPointerTy(DAG.getDataLayout()) &&
"Memory operands expect pointer values");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
}
if (OpInfo.ConstraintType == TargetLowering::C_Address) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a7873241df62e52..91b9d77eed70596 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2101,7 +2101,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector &Ops,
// Otherwise, this is a memory operand. Ask the target to select it.
std::vector SelOps;
- unsigned ConstraintID = Flags.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode ConstraintID =
+ Flags.getMemoryConstraintID();
if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
report_fatal_error("Could not match memory address. Inline asm"
" failure!");
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 686044ea572ac0d..bf1605f06bd88d6 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 60a155a86667e89..740995849740fef 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -61,9 +61,10 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
template
bool SelectRDVLImm(SDValue N, SDValue &Imm);
@@ -533,13 +534,14 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
#endif
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 67c344318e0d3ec..f2696b6b97593a1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1169,9 +1169,10 @@ class AArch64TargetLowering : public TargetLowering {
std::vector &Ops,
SelectionDAG &DAG) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
// followed by llvm_unreachable so we'll leave them unimplemented in
// the backend for now.
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 5f4fab0675824fd..9956b1b040b329d 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -331,8 +331,10 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
// Form pairs of consecutive R, S, D, or Q registers.
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
@@ -5864,23 +5866,22 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
return true;
}
-
-bool ARMDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) {
+bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
- case InlineAsm::Constraint_Um:
- case InlineAsm::Constraint_Un:
- case InlineAsm::Constraint_Uq:
- case InlineAsm::Constraint_Us:
- case InlineAsm::Constraint_Ut:
- case InlineAsm::Constraint_Uv:
- case InlineAsm::Constraint_Uy:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::ConstraintCode::Um:
+ case InlineAsm::ConstraintCode::Un:
+ case InlineAsm::ConstraintCode::Uq:
+ case InlineAsm::ConstraintCode::Us:
+ case InlineAsm::ConstraintCod...
|
|
@llvm/pr-subscribers-llvm-ir ChangesSimilar to Fix the TODOs added in -- Patch is 34.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66003.diff 25 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 557c6ef03d96b98..d3907865a659121 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -89,9 +89,10 @@ class SelectionDAGISel : public MachineFunctionPass {
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) {
+ virtual bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
return true;
}
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 12b280d5b1a0bcd..f4feab495932294 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4833,16 +4833,17 @@ class TargetLowering : public TargetLoweringBase {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const;
- virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+ virtual InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const {
if (ConstraintCode == "m")
- return InlineAsm::Constraint_m;
+ return InlineAsm::ConstraintCode::m;
if (ConstraintCode == "o")
- return InlineAsm::Constraint_o;
+ return InlineAsm::ConstraintCode::o;
if (ConstraintCode == "X")
- return InlineAsm::Constraint_X;
+ return InlineAsm::ConstraintCode::X;
if (ConstraintCode == "p")
- return InlineAsm::Constraint_p;
- return InlineAsm::Constraint_Unknown;
+ return InlineAsm::ConstraintCode::p;
+ return InlineAsm::ConstraintCode::Unknown;
}
/// Try to replace an X constraint, which matches anything, with another that
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index f73666fa8dc08e7..a4032ce7abde331 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -217,48 +217,6 @@ class InlineAsm final : public Value {
Extra_MayLoad = 8,
Extra_MayStore = 16,
Extra_IsConvergent = 32,
-
- // Memory constraint codes.
- // These could be tablegenerated but there's little need to do that since
- // there's plenty of space in the encoding to support the union of all
- // constraint codes for all targets.
- // Addresses are included here as they need to be treated the same by the
- // backend, the only difference is that they are not used to actaully
- // access memory by the instruction.
- // TODO: convert to enum?
- Constraint_Unknown = 0,
- Constraint_es,
- Constraint_i,
- Constraint_k,
- Constraint_m,
- Constraint_o,
- Constraint_v,
- Constraint_A,
- Constraint_Q,
- Constraint_R,
- Constraint_S,
- Constraint_T,
- Constraint_Um,
- Constraint_Un,
- Constraint_Uq,
- Constraint_Us,
- Constraint_Ut,
- Constraint_Uv,
- Constraint_Uy,
- Constraint_X,
- Constraint_Z,
- Constraint_ZB,
- Constraint_ZC,
- Constraint_Zy,
-
- // Address constraints
- Constraint_p,
- Constraint_ZQ,
- Constraint_ZR,
- Constraint_ZS,
- Constraint_ZT,
-
- Constraints_Max = Constraint_ZT,
};
// Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -274,6 +232,46 @@ class InlineAsm final : public Value {
Func = 7, // Address operand of function call
};
+ // Memory constraint codes.
+ // Addresses are included here as they need to be treated the same by the
+ // backend, the only difference is that they are not used to actaully
+ // access memory by the instruction.
+ enum class ConstraintCode : uint32_t {
+ Unknown = 0,
+ es,
+ i,
+ k,
+ m,
+ o,
+ v,
+ A,
+ Q,
+ R,
+ S,
+ T,
+ Um,
+ Un,
+ Uq,
+ Us,
+ Ut,
+ Uv,
+ Uy,
+ X,
+ Z,
+ ZB,
+ ZC,
+ Zy,
+
+ // Address constraints
+ p,
+ ZQ,
+ ZR,
+ ZS,
+ ZT,
+
+ Max = ZT,
+ };
+
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
//
@@ -375,11 +373,14 @@ class InlineAsm final : public Value {
return true;
}
- // TODO: convert to enum?
- unsigned getMemoryConstraintID() const {
+ ConstraintCode getMemoryConstraintID() const {
assert((isMemKind() || isFuncKind()) &&
"Not expected mem or function flag!");
- return getData();
+ uint32_t D = getData();
+ assert(D < static_cast(ConstraintCode::Max) &&
+ D >= static_cast(ConstraintCode::Unknown) &&
+ "unexpected value for memory constraint");
+ return static_cast(D);
}
/// setMatchingOp - Augment an existing flag with information indicating
@@ -403,12 +404,11 @@ class InlineAsm final : public Value {
/// setMemConstraint - Augment an existing flag with the constraint code for
/// a memory constraint.
- void setMemConstraint(unsigned Constraint) {
+ void setMemConstraint(ConstraintCode C) {
assert((isMemKind() || isFuncKind()) &&
"Flag is not a memory or function constraint!");
- assert(Constraint <= Constraints_Max && "Unknown constraint ID");
assert(getData() == 0 && "Mem constraint already set");
- setData(Constraint);
+ setData(static_cast(C));
}
/// clearMemConstraint - Similar to setMemConstraint(0), but without the
/// assertion checking that the constraint has not been set previously.
@@ -443,61 +443,61 @@ class InlineAsm final : public Value {
return Result;
}
- static StringRef getMemConstraintName(unsigned Constraint) {
- switch (Constraint) {
- case InlineAsm::Constraint_es:
+ static StringRef getMemConstraintName(const ConstraintCode C) {
+ switch (C) {
+ case ConstraintCode::es:
return "es";
- case InlineAsm::Constraint_i:
+ case ConstraintCode::i:
return "i";
- case InlineAsm::Constraint_k:
+ case ConstraintCode::k:
return "k";
- case InlineAsm::Constraint_m:
+ case ConstraintCode::m:
return "m";
- case InlineAsm::Constraint_o:
+ case ConstraintCode::o:
return "o";
- case InlineAsm::Constraint_v:
+ case ConstraintCode::v:
return "v";
- case InlineAsm::Constraint_Q:
+ case ConstraintCode::Q:
return "Q";
- case InlineAsm::Constraint_R:
+ case ConstraintCode::R:
return "R";
- case InlineAsm::Constraint_S:
+ case ConstraintCode::S:
return "S";
- case InlineAsm::Constraint_T:
+ case ConstraintCode::T:
return "T";
- case InlineAsm::Constraint_Um:
+ case ConstraintCode::Um:
return "Um";
- case InlineAsm::Constraint_Un:
+ case ConstraintCode::Un:
return "Un";
- case InlineAsm::Constraint_Uq:
+ case ConstraintCode::Uq:
return "Uq";
- case InlineAsm::Constraint_Us:
+ case ConstraintCode::Us:
return "Us";
- case InlineAsm::Constraint_Ut:
+ case ConstraintCode::Ut:
return "Ut";
- case InlineAsm::Constraint_Uv:
+ case ConstraintCode::Uv:
return "Uv";
- case InlineAsm::Constraint_Uy:
+ case ConstraintCode::Uy:
return "Uy";
- case InlineAsm::Constraint_X:
+ case ConstraintCode::X:
return "X";
- case InlineAsm::Constraint_Z:
+ case ConstraintCode::Z:
return "Z";
- case InlineAsm::Constraint_ZB:
+ case ConstraintCode::ZB:
return "ZB";
- case InlineAsm::Constraint_ZC:
+ case ConstraintCode::ZC:
return "ZC";
- case InlineAsm::Constraint_Zy:
+ case ConstraintCode::Zy:
return "Zy";
- case InlineAsm::Constraint_p:
+ case ConstraintCode::p:
return "p";
- case InlineAsm::Constraint_ZQ:
+ case ConstraintCode::ZQ:
return "ZQ";
- case InlineAsm::Constraint_ZR:
+ case ConstraintCode::ZR:
return "ZR";
- case InlineAsm::Constraint_ZS:
+ case ConstraintCode::ZS:
return "ZS";
- case InlineAsm::Constraint_ZT:
+ case ConstraintCode::ZT:
return "ZT";
default:
llvm_unreachable("Unknown memory constraint");
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 9944ba15997687a..00dba57fcb80227 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
OpFlags.setMemConstraint(ConstraintID);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 8cc3391e0d96a3d..d8467e2af8786ec 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 738dd10633db6a5..720fc4944161225 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
TLI.getPointerTy(DAG.getDataLayout()) &&
"Memory operands expect pointer values");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
}
if (OpInfo.ConstraintType == TargetLowering::C_Address) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a7873241df62e52..91b9d77eed70596 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2101,7 +2101,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector &Ops,
// Otherwise, this is a memory operand. Ask the target to select it.
std::vector SelOps;
- unsigned ConstraintID = Flags.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode ConstraintID =
+ Flags.getMemoryConstraintID();
if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
report_fatal_error("Could not match memory address. Inline asm"
" failure!");
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 686044ea572ac0d..bf1605f06bd88d6 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 60a155a86667e89..740995849740fef 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -61,9 +61,10 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
template
bool SelectRDVLImm(SDValue N, SDValue &Imm);
@@ -533,13 +534,14 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
#endif
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 67c344318e0d3ec..f2696b6b97593a1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1169,9 +1169,10 @@ class AArch64TargetLowering : public TargetLowering {
std::vector &Ops,
SelectionDAG &DAG) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
// followed by llvm_unreachable so we'll leave them unimplemented in
// the backend for now.
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 5f4fab0675824fd..9956b1b040b329d 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -331,8 +331,10 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
// Form pairs of consecutive R, S, D, or Q registers.
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
@@ -5864,23 +5866,22 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
return true;
}
-
-bool ARMDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) {
+bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
- case InlineAsm::Constraint_Um:
- case InlineAsm::Constraint_Un:
- case InlineAsm::Constraint_Uq:
- case InlineAsm::Constraint_Us:
- case InlineAsm::Constraint_Ut:
- case InlineAsm::Constraint_Uv:
- case InlineAsm::Constraint_Uy:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::ConstraintCode::Um:
+ case InlineAsm::ConstraintCode::Un:
+ case InlineAsm::ConstraintCode::Uq:
+ case InlineAsm::ConstraintCode::Us:
+ case InlineAsm::ConstraintCod...
|
|
@llvm/pr-subscribers-llvm-selectiondag ChangesSimilar to Fix the TODOs added in -- Patch is 34.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66003.diff 25 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 557c6ef03d96b98..d3907865a659121 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -89,9 +89,10 @@ class SelectionDAGISel : public MachineFunctionPass {
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) {
+ virtual bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
return true;
}
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 12b280d5b1a0bcd..f4feab495932294 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4833,16 +4833,17 @@ class TargetLowering : public TargetLoweringBase {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const;
- virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+ virtual InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const {
if (ConstraintCode == "m")
- return InlineAsm::Constraint_m;
+ return InlineAsm::ConstraintCode::m;
if (ConstraintCode == "o")
- return InlineAsm::Constraint_o;
+ return InlineAsm::ConstraintCode::o;
if (ConstraintCode == "X")
- return InlineAsm::Constraint_X;
+ return InlineAsm::ConstraintCode::X;
if (ConstraintCode == "p")
- return InlineAsm::Constraint_p;
- return InlineAsm::Constraint_Unknown;
+ return InlineAsm::ConstraintCode::p;
+ return InlineAsm::ConstraintCode::Unknown;
}
/// Try to replace an X constraint, which matches anything, with another that
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index f73666fa8dc08e7..a4032ce7abde331 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -217,48 +217,6 @@ class InlineAsm final : public Value {
Extra_MayLoad = 8,
Extra_MayStore = 16,
Extra_IsConvergent = 32,
-
- // Memory constraint codes.
- // These could be tablegenerated but there's little need to do that since
- // there's plenty of space in the encoding to support the union of all
- // constraint codes for all targets.
- // Addresses are included here as they need to be treated the same by the
- // backend, the only difference is that they are not used to actaully
- // access memory by the instruction.
- // TODO: convert to enum?
- Constraint_Unknown = 0,
- Constraint_es,
- Constraint_i,
- Constraint_k,
- Constraint_m,
- Constraint_o,
- Constraint_v,
- Constraint_A,
- Constraint_Q,
- Constraint_R,
- Constraint_S,
- Constraint_T,
- Constraint_Um,
- Constraint_Un,
- Constraint_Uq,
- Constraint_Us,
- Constraint_Ut,
- Constraint_Uv,
- Constraint_Uy,
- Constraint_X,
- Constraint_Z,
- Constraint_ZB,
- Constraint_ZC,
- Constraint_Zy,
-
- // Address constraints
- Constraint_p,
- Constraint_ZQ,
- Constraint_ZR,
- Constraint_ZS,
- Constraint_ZT,
-
- Constraints_Max = Constraint_ZT,
};
// Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -274,6 +232,46 @@ class InlineAsm final : public Value {
Func = 7, // Address operand of function call
};
+ // Memory constraint codes.
+ // Addresses are included here as they need to be treated the same by the
+ // backend, the only difference is that they are not used to actaully
+ // access memory by the instruction.
+ enum class ConstraintCode : uint32_t {
+ Unknown = 0,
+ es,
+ i,
+ k,
+ m,
+ o,
+ v,
+ A,
+ Q,
+ R,
+ S,
+ T,
+ Um,
+ Un,
+ Uq,
+ Us,
+ Ut,
+ Uv,
+ Uy,
+ X,
+ Z,
+ ZB,
+ ZC,
+ Zy,
+
+ // Address constraints
+ p,
+ ZQ,
+ ZR,
+ ZS,
+ ZT,
+
+ Max = ZT,
+ };
+
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
//
@@ -375,11 +373,14 @@ class InlineAsm final : public Value {
return true;
}
- // TODO: convert to enum?
- unsigned getMemoryConstraintID() const {
+ ConstraintCode getMemoryConstraintID() const {
assert((isMemKind() || isFuncKind()) &&
"Not expected mem or function flag!");
- return getData();
+ uint32_t D = getData();
+ assert(D < static_cast(ConstraintCode::Max) &&
+ D >= static_cast(ConstraintCode::Unknown) &&
+ "unexpected value for memory constraint");
+ return static_cast(D);
}
/// setMatchingOp - Augment an existing flag with information indicating
@@ -403,12 +404,11 @@ class InlineAsm final : public Value {
/// setMemConstraint - Augment an existing flag with the constraint code for
/// a memory constraint.
- void setMemConstraint(unsigned Constraint) {
+ void setMemConstraint(ConstraintCode C) {
assert((isMemKind() || isFuncKind()) &&
"Flag is not a memory or function constraint!");
- assert(Constraint <= Constraints_Max && "Unknown constraint ID");
assert(getData() == 0 && "Mem constraint already set");
- setData(Constraint);
+ setData(static_cast(C));
}
/// clearMemConstraint - Similar to setMemConstraint(0), but without the
/// assertion checking that the constraint has not been set previously.
@@ -443,61 +443,61 @@ class InlineAsm final : public Value {
return Result;
}
- static StringRef getMemConstraintName(unsigned Constraint) {
- switch (Constraint) {
- case InlineAsm::Constraint_es:
+ static StringRef getMemConstraintName(const ConstraintCode C) {
+ switch (C) {
+ case ConstraintCode::es:
return "es";
- case InlineAsm::Constraint_i:
+ case ConstraintCode::i:
return "i";
- case InlineAsm::Constraint_k:
+ case ConstraintCode::k:
return "k";
- case InlineAsm::Constraint_m:
+ case ConstraintCode::m:
return "m";
- case InlineAsm::Constraint_o:
+ case ConstraintCode::o:
return "o";
- case InlineAsm::Constraint_v:
+ case ConstraintCode::v:
return "v";
- case InlineAsm::Constraint_Q:
+ case ConstraintCode::Q:
return "Q";
- case InlineAsm::Constraint_R:
+ case ConstraintCode::R:
return "R";
- case InlineAsm::Constraint_S:
+ case ConstraintCode::S:
return "S";
- case InlineAsm::Constraint_T:
+ case ConstraintCode::T:
return "T";
- case InlineAsm::Constraint_Um:
+ case ConstraintCode::Um:
return "Um";
- case InlineAsm::Constraint_Un:
+ case ConstraintCode::Un:
return "Un";
- case InlineAsm::Constraint_Uq:
+ case ConstraintCode::Uq:
return "Uq";
- case InlineAsm::Constraint_Us:
+ case ConstraintCode::Us:
return "Us";
- case InlineAsm::Constraint_Ut:
+ case ConstraintCode::Ut:
return "Ut";
- case InlineAsm::Constraint_Uv:
+ case ConstraintCode::Uv:
return "Uv";
- case InlineAsm::Constraint_Uy:
+ case ConstraintCode::Uy:
return "Uy";
- case InlineAsm::Constraint_X:
+ case ConstraintCode::X:
return "X";
- case InlineAsm::Constraint_Z:
+ case ConstraintCode::Z:
return "Z";
- case InlineAsm::Constraint_ZB:
+ case ConstraintCode::ZB:
return "ZB";
- case InlineAsm::Constraint_ZC:
+ case ConstraintCode::ZC:
return "ZC";
- case InlineAsm::Constraint_Zy:
+ case ConstraintCode::Zy:
return "Zy";
- case InlineAsm::Constraint_p:
+ case ConstraintCode::p:
return "p";
- case InlineAsm::Constraint_ZQ:
+ case ConstraintCode::ZQ:
return "ZQ";
- case InlineAsm::Constraint_ZR:
+ case ConstraintCode::ZR:
return "ZR";
- case InlineAsm::Constraint_ZS:
+ case ConstraintCode::ZS:
return "ZS";
- case InlineAsm::Constraint_ZT:
+ case ConstraintCode::ZT:
return "ZT";
default:
llvm_unreachable("Unknown memory constraint");
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 9944ba15997687a..00dba57fcb80227 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
OpFlags.setMemConstraint(ConstraintID);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 8cc3391e0d96a3d..d8467e2af8786ec 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 738dd10633db6a5..720fc4944161225 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
TLI.getPointerTy(DAG.getDataLayout()) &&
"Memory operands expect pointer values");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
}
if (OpInfo.ConstraintType == TargetLowering::C_Address) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a7873241df62e52..91b9d77eed70596 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2101,7 +2101,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector &Ops,
// Otherwise, this is a memory operand. Ask the target to select it.
std::vector SelOps;
- unsigned ConstraintID = Flags.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode ConstraintID =
+ Flags.getMemoryConstraintID();
if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
report_fatal_error("Could not match memory address. Inline asm"
" failure!");
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 686044ea572ac0d..bf1605f06bd88d6 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 60a155a86667e89..740995849740fef 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -61,9 +61,10 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
template
bool SelectRDVLImm(SDValue N, SDValue &Imm);
@@ -533,13 +534,14 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
#endif
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 67c344318e0d3ec..f2696b6b97593a1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1169,9 +1169,10 @@ class AArch64TargetLowering : public TargetLowering {
std::vector &Ops,
SelectionDAG &DAG) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
// followed by llvm_unreachable so we'll leave them unimplemented in
// the backend for now.
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 5f4fab0675824fd..9956b1b040b329d 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -331,8 +331,10 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
// Form pairs of consecutive R, S, D, or Q registers.
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
@@ -5864,23 +5866,22 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
return true;
}
-
-bool ARMDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) {
+bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
- case InlineAsm::Constraint_Um:
- case InlineAsm::Constraint_Un:
- case InlineAsm::Constraint_Uq:
- case InlineAsm::Constraint_Us:
- case InlineAsm::Constraint_Ut:
- case InlineAsm::Constraint_Uv:
- case InlineAsm::Constraint_Uy:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::ConstraintCode::Um:
+ case InlineAsm::ConstraintCode::Un:
+ case InlineAsm::ConstraintCode::Uq:
+ case InlineAsm::ConstraintCode::Us:
+ case InlineAsm::ConstraintCod...
|
|
@llvm/pr-subscribers-backend-arm ChangesSimilar to Fix the TODOs added in -- Patch is 34.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66003.diff 25 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 557c6ef03d96b98..d3907865a659121 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -89,9 +89,10 @@ class SelectionDAGISel : public MachineFunctionPass {
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) {
+ virtual bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
return true;
}
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 12b280d5b1a0bcd..f4feab495932294 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4833,16 +4833,17 @@ class TargetLowering : public TargetLoweringBase {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const;
- virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+ virtual InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const {
if (ConstraintCode == "m")
- return InlineAsm::Constraint_m;
+ return InlineAsm::ConstraintCode::m;
if (ConstraintCode == "o")
- return InlineAsm::Constraint_o;
+ return InlineAsm::ConstraintCode::o;
if (ConstraintCode == "X")
- return InlineAsm::Constraint_X;
+ return InlineAsm::ConstraintCode::X;
if (ConstraintCode == "p")
- return InlineAsm::Constraint_p;
- return InlineAsm::Constraint_Unknown;
+ return InlineAsm::ConstraintCode::p;
+ return InlineAsm::ConstraintCode::Unknown;
}
/// Try to replace an X constraint, which matches anything, with another that
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index f73666fa8dc08e7..a4032ce7abde331 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -217,48 +217,6 @@ class InlineAsm final : public Value {
Extra_MayLoad = 8,
Extra_MayStore = 16,
Extra_IsConvergent = 32,
-
- // Memory constraint codes.
- // These could be tablegenerated but there's little need to do that since
- // there's plenty of space in the encoding to support the union of all
- // constraint codes for all targets.
- // Addresses are included here as they need to be treated the same by the
- // backend, the only difference is that they are not used to actaully
- // access memory by the instruction.
- // TODO: convert to enum?
- Constraint_Unknown = 0,
- Constraint_es,
- Constraint_i,
- Constraint_k,
- Constraint_m,
- Constraint_o,
- Constraint_v,
- Constraint_A,
- Constraint_Q,
- Constraint_R,
- Constraint_S,
- Constraint_T,
- Constraint_Um,
- Constraint_Un,
- Constraint_Uq,
- Constraint_Us,
- Constraint_Ut,
- Constraint_Uv,
- Constraint_Uy,
- Constraint_X,
- Constraint_Z,
- Constraint_ZB,
- Constraint_ZC,
- Constraint_Zy,
-
- // Address constraints
- Constraint_p,
- Constraint_ZQ,
- Constraint_ZR,
- Constraint_ZS,
- Constraint_ZT,
-
- Constraints_Max = Constraint_ZT,
};
// Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -274,6 +232,46 @@ class InlineAsm final : public Value {
Func = 7, // Address operand of function call
};
+ // Memory constraint codes.
+ // Addresses are included here as they need to be treated the same by the
+ // backend, the only difference is that they are not used to actaully
+ // access memory by the instruction.
+ enum class ConstraintCode : uint32_t {
+ Unknown = 0,
+ es,
+ i,
+ k,
+ m,
+ o,
+ v,
+ A,
+ Q,
+ R,
+ S,
+ T,
+ Um,
+ Un,
+ Uq,
+ Us,
+ Ut,
+ Uv,
+ Uy,
+ X,
+ Z,
+ ZB,
+ ZC,
+ Zy,
+
+ // Address constraints
+ p,
+ ZQ,
+ ZR,
+ ZS,
+ ZT,
+
+ Max = ZT,
+ };
+
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
//
@@ -375,11 +373,14 @@ class InlineAsm final : public Value {
return true;
}
- // TODO: convert to enum?
- unsigned getMemoryConstraintID() const {
+ ConstraintCode getMemoryConstraintID() const {
assert((isMemKind() || isFuncKind()) &&
"Not expected mem or function flag!");
- return getData();
+ uint32_t D = getData();
+ assert(D < static_cast(ConstraintCode::Max) &&
+ D >= static_cast(ConstraintCode::Unknown) &&
+ "unexpected value for memory constraint");
+ return static_cast(D);
}
/// setMatchingOp - Augment an existing flag with information indicating
@@ -403,12 +404,11 @@ class InlineAsm final : public Value {
/// setMemConstraint - Augment an existing flag with the constraint code for
/// a memory constraint.
- void setMemConstraint(unsigned Constraint) {
+ void setMemConstraint(ConstraintCode C) {
assert((isMemKind() || isFuncKind()) &&
"Flag is not a memory or function constraint!");
- assert(Constraint <= Constraints_Max && "Unknown constraint ID");
assert(getData() == 0 && "Mem constraint already set");
- setData(Constraint);
+ setData(static_cast(C));
}
/// clearMemConstraint - Similar to setMemConstraint(0), but without the
/// assertion checking that the constraint has not been set previously.
@@ -443,61 +443,61 @@ class InlineAsm final : public Value {
return Result;
}
- static StringRef getMemConstraintName(unsigned Constraint) {
- switch (Constraint) {
- case InlineAsm::Constraint_es:
+ static StringRef getMemConstraintName(const ConstraintCode C) {
+ switch (C) {
+ case ConstraintCode::es:
return "es";
- case InlineAsm::Constraint_i:
+ case ConstraintCode::i:
return "i";
- case InlineAsm::Constraint_k:
+ case ConstraintCode::k:
return "k";
- case InlineAsm::Constraint_m:
+ case ConstraintCode::m:
return "m";
- case InlineAsm::Constraint_o:
+ case ConstraintCode::o:
return "o";
- case InlineAsm::Constraint_v:
+ case ConstraintCode::v:
return "v";
- case InlineAsm::Constraint_Q:
+ case ConstraintCode::Q:
return "Q";
- case InlineAsm::Constraint_R:
+ case ConstraintCode::R:
return "R";
- case InlineAsm::Constraint_S:
+ case ConstraintCode::S:
return "S";
- case InlineAsm::Constraint_T:
+ case ConstraintCode::T:
return "T";
- case InlineAsm::Constraint_Um:
+ case ConstraintCode::Um:
return "Um";
- case InlineAsm::Constraint_Un:
+ case ConstraintCode::Un:
return "Un";
- case InlineAsm::Constraint_Uq:
+ case ConstraintCode::Uq:
return "Uq";
- case InlineAsm::Constraint_Us:
+ case ConstraintCode::Us:
return "Us";
- case InlineAsm::Constraint_Ut:
+ case ConstraintCode::Ut:
return "Ut";
- case InlineAsm::Constraint_Uv:
+ case ConstraintCode::Uv:
return "Uv";
- case InlineAsm::Constraint_Uy:
+ case ConstraintCode::Uy:
return "Uy";
- case InlineAsm::Constraint_X:
+ case ConstraintCode::X:
return "X";
- case InlineAsm::Constraint_Z:
+ case ConstraintCode::Z:
return "Z";
- case InlineAsm::Constraint_ZB:
+ case ConstraintCode::ZB:
return "ZB";
- case InlineAsm::Constraint_ZC:
+ case ConstraintCode::ZC:
return "ZC";
- case InlineAsm::Constraint_Zy:
+ case ConstraintCode::Zy:
return "Zy";
- case InlineAsm::Constraint_p:
+ case ConstraintCode::p:
return "p";
- case InlineAsm::Constraint_ZQ:
+ case ConstraintCode::ZQ:
return "ZQ";
- case InlineAsm::Constraint_ZR:
+ case ConstraintCode::ZR:
return "ZR";
- case InlineAsm::Constraint_ZS:
+ case ConstraintCode::ZS:
return "ZS";
- case InlineAsm::Constraint_ZT:
+ case ConstraintCode::ZT:
return "ZT";
default:
llvm_unreachable("Unknown memory constraint");
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 9944ba15997687a..00dba57fcb80227 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
OpFlags.setMemConstraint(ConstraintID);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 8cc3391e0d96a3d..d8467e2af8786ec 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 738dd10633db6a5..720fc4944161225 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
TLI.getPointerTy(DAG.getDataLayout()) &&
"Memory operands expect pointer values");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
}
if (OpInfo.ConstraintType == TargetLowering::C_Address) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a7873241df62e52..91b9d77eed70596 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2101,7 +2101,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector &Ops,
// Otherwise, this is a memory operand. Ask the target to select it.
std::vector SelOps;
- unsigned ConstraintID = Flags.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode ConstraintID =
+ Flags.getMemoryConstraintID();
if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
report_fatal_error("Could not match memory address. Inline asm"
" failure!");
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 686044ea572ac0d..bf1605f06bd88d6 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 60a155a86667e89..740995849740fef 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -61,9 +61,10 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
template
bool SelectRDVLImm(SDValue N, SDValue &Imm);
@@ -533,13 +534,14 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
#endif
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 67c344318e0d3ec..f2696b6b97593a1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1169,9 +1169,10 @@ class AArch64TargetLowering : public TargetLowering {
std::vector &Ops,
SelectionDAG &DAG) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
// followed by llvm_unreachable so we'll leave them unimplemented in
// the backend for now.
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 5f4fab0675824fd..9956b1b040b329d 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -331,8 +331,10 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
// Form pairs of consecutive R, S, D, or Q registers.
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
@@ -5864,23 +5866,22 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
return true;
}
-
-bool ARMDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) {
+bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
- case InlineAsm::Constraint_Um:
- case InlineAsm::Constraint_Un:
- case InlineAsm::Constraint_Uq:
- case InlineAsm::Constraint_Us:
- case InlineAsm::Constraint_Ut:
- case InlineAsm::Constraint_Uv:
- case InlineAsm::Constraint_Uy:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::ConstraintCode::Um:
+ case InlineAsm::ConstraintCode::Un:
+ case InlineAsm::ConstraintCode::Uq:
+ case InlineAsm::ConstraintCode::Us:
+ case InlineAsm::ConstraintCod...
|
|
@llvm/pr-subscribers-llvm-globalisel ChangesSimilar to Fix the TODOs added in -- Patch is 34.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66003.diff 25 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 557c6ef03d96b98..d3907865a659121 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -89,9 +89,10 @@ class SelectionDAGISel : public MachineFunctionPass {
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) {
+ virtual bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
return true;
}
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 12b280d5b1a0bcd..f4feab495932294 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4833,16 +4833,17 @@ class TargetLowering : public TargetLoweringBase {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const;
- virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+ virtual InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const {
if (ConstraintCode == "m")
- return InlineAsm::Constraint_m;
+ return InlineAsm::ConstraintCode::m;
if (ConstraintCode == "o")
- return InlineAsm::Constraint_o;
+ return InlineAsm::ConstraintCode::o;
if (ConstraintCode == "X")
- return InlineAsm::Constraint_X;
+ return InlineAsm::ConstraintCode::X;
if (ConstraintCode == "p")
- return InlineAsm::Constraint_p;
- return InlineAsm::Constraint_Unknown;
+ return InlineAsm::ConstraintCode::p;
+ return InlineAsm::ConstraintCode::Unknown;
}
/// Try to replace an X constraint, which matches anything, with another that
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index f73666fa8dc08e7..a4032ce7abde331 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -217,48 +217,6 @@ class InlineAsm final : public Value {
Extra_MayLoad = 8,
Extra_MayStore = 16,
Extra_IsConvergent = 32,
-
- // Memory constraint codes.
- // These could be tablegenerated but there's little need to do that since
- // there's plenty of space in the encoding to support the union of all
- // constraint codes for all targets.
- // Addresses are included here as they need to be treated the same by the
- // backend, the only difference is that they are not used to actaully
- // access memory by the instruction.
- // TODO: convert to enum?
- Constraint_Unknown = 0,
- Constraint_es,
- Constraint_i,
- Constraint_k,
- Constraint_m,
- Constraint_o,
- Constraint_v,
- Constraint_A,
- Constraint_Q,
- Constraint_R,
- Constraint_S,
- Constraint_T,
- Constraint_Um,
- Constraint_Un,
- Constraint_Uq,
- Constraint_Us,
- Constraint_Ut,
- Constraint_Uv,
- Constraint_Uy,
- Constraint_X,
- Constraint_Z,
- Constraint_ZB,
- Constraint_ZC,
- Constraint_Zy,
-
- // Address constraints
- Constraint_p,
- Constraint_ZQ,
- Constraint_ZR,
- Constraint_ZS,
- Constraint_ZT,
-
- Constraints_Max = Constraint_ZT,
};
// Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -274,6 +232,46 @@ class InlineAsm final : public Value {
Func = 7, // Address operand of function call
};
+ // Memory constraint codes.
+ // Addresses are included here as they need to be treated the same by the
+ // backend, the only difference is that they are not used to actaully
+ // access memory by the instruction.
+ enum class ConstraintCode : uint32_t {
+ Unknown = 0,
+ es,
+ i,
+ k,
+ m,
+ o,
+ v,
+ A,
+ Q,
+ R,
+ S,
+ T,
+ Um,
+ Un,
+ Uq,
+ Us,
+ Ut,
+ Uv,
+ Uy,
+ X,
+ Z,
+ ZB,
+ ZC,
+ Zy,
+
+ // Address constraints
+ p,
+ ZQ,
+ ZR,
+ ZS,
+ ZT,
+
+ Max = ZT,
+ };
+
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
//
@@ -375,11 +373,14 @@ class InlineAsm final : public Value {
return true;
}
- // TODO: convert to enum?
- unsigned getMemoryConstraintID() const {
+ ConstraintCode getMemoryConstraintID() const {
assert((isMemKind() || isFuncKind()) &&
"Not expected mem or function flag!");
- return getData();
+ uint32_t D = getData();
+ assert(D < static_cast(ConstraintCode::Max) &&
+ D >= static_cast(ConstraintCode::Unknown) &&
+ "unexpected value for memory constraint");
+ return static_cast(D);
}
/// setMatchingOp - Augment an existing flag with information indicating
@@ -403,12 +404,11 @@ class InlineAsm final : public Value {
/// setMemConstraint - Augment an existing flag with the constraint code for
/// a memory constraint.
- void setMemConstraint(unsigned Constraint) {
+ void setMemConstraint(ConstraintCode C) {
assert((isMemKind() || isFuncKind()) &&
"Flag is not a memory or function constraint!");
- assert(Constraint <= Constraints_Max && "Unknown constraint ID");
assert(getData() == 0 && "Mem constraint already set");
- setData(Constraint);
+ setData(static_cast(C));
}
/// clearMemConstraint - Similar to setMemConstraint(0), but without the
/// assertion checking that the constraint has not been set previously.
@@ -443,61 +443,61 @@ class InlineAsm final : public Value {
return Result;
}
- static StringRef getMemConstraintName(unsigned Constraint) {
- switch (Constraint) {
- case InlineAsm::Constraint_es:
+ static StringRef getMemConstraintName(const ConstraintCode C) {
+ switch (C) {
+ case ConstraintCode::es:
return "es";
- case InlineAsm::Constraint_i:
+ case ConstraintCode::i:
return "i";
- case InlineAsm::Constraint_k:
+ case ConstraintCode::k:
return "k";
- case InlineAsm::Constraint_m:
+ case ConstraintCode::m:
return "m";
- case InlineAsm::Constraint_o:
+ case ConstraintCode::o:
return "o";
- case InlineAsm::Constraint_v:
+ case ConstraintCode::v:
return "v";
- case InlineAsm::Constraint_Q:
+ case ConstraintCode::Q:
return "Q";
- case InlineAsm::Constraint_R:
+ case ConstraintCode::R:
return "R";
- case InlineAsm::Constraint_S:
+ case ConstraintCode::S:
return "S";
- case InlineAsm::Constraint_T:
+ case ConstraintCode::T:
return "T";
- case InlineAsm::Constraint_Um:
+ case ConstraintCode::Um:
return "Um";
- case InlineAsm::Constraint_Un:
+ case ConstraintCode::Un:
return "Un";
- case InlineAsm::Constraint_Uq:
+ case ConstraintCode::Uq:
return "Uq";
- case InlineAsm::Constraint_Us:
+ case ConstraintCode::Us:
return "Us";
- case InlineAsm::Constraint_Ut:
+ case ConstraintCode::Ut:
return "Ut";
- case InlineAsm::Constraint_Uv:
+ case ConstraintCode::Uv:
return "Uv";
- case InlineAsm::Constraint_Uy:
+ case ConstraintCode::Uy:
return "Uy";
- case InlineAsm::Constraint_X:
+ case ConstraintCode::X:
return "X";
- case InlineAsm::Constraint_Z:
+ case ConstraintCode::Z:
return "Z";
- case InlineAsm::Constraint_ZB:
+ case ConstraintCode::ZB:
return "ZB";
- case InlineAsm::Constraint_ZC:
+ case ConstraintCode::ZC:
return "ZC";
- case InlineAsm::Constraint_Zy:
+ case ConstraintCode::Zy:
return "Zy";
- case InlineAsm::Constraint_p:
+ case ConstraintCode::p:
return "p";
- case InlineAsm::Constraint_ZQ:
+ case ConstraintCode::ZQ:
return "ZQ";
- case InlineAsm::Constraint_ZR:
+ case ConstraintCode::ZR:
return "ZR";
- case InlineAsm::Constraint_ZS:
+ case ConstraintCode::ZS:
return "ZS";
- case InlineAsm::Constraint_ZT:
+ case ConstraintCode::ZT:
return "ZT";
default:
llvm_unreachable("Unknown memory constraint");
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 9944ba15997687a..00dba57fcb80227 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
OpFlags.setMemConstraint(ConstraintID);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 8cc3391e0d96a3d..d8467e2af8786ec 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 738dd10633db6a5..720fc4944161225 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
TLI.getPointerTy(DAG.getDataLayout()) &&
"Memory operands expect pointer values");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
}
if (OpInfo.ConstraintType == TargetLowering::C_Address) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a7873241df62e52..91b9d77eed70596 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2101,7 +2101,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector &Ops,
// Otherwise, this is a memory operand. Ask the target to select it.
std::vector SelOps;
- unsigned ConstraintID = Flags.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode ConstraintID =
+ Flags.getMemoryConstraintID();
if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
report_fatal_error("Could not match memory address. Inline asm"
" failure!");
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 686044ea572ac0d..bf1605f06bd88d6 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 60a155a86667e89..740995849740fef 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -61,9 +61,10 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
template
bool SelectRDVLImm(SDValue N, SDValue &Imm);
@@ -533,13 +534,14 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
#endif
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 67c344318e0d3ec..f2696b6b97593a1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1169,9 +1169,10 @@ class AArch64TargetLowering : public TargetLowering {
std::vector &Ops,
SelectionDAG &DAG) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
// followed by llvm_unreachable so we'll leave them unimplemented in
// the backend for now.
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 5f4fab0675824fd..9956b1b040b329d 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -331,8 +331,10 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
// Form pairs of consecutive R, S, D, or Q registers.
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
@@ -5864,23 +5866,22 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
return true;
}
-
-bool ARMDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) {
+bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
- case InlineAsm::Constraint_Um:
- case InlineAsm::Constraint_Un:
- case InlineAsm::Constraint_Uq:
- case InlineAsm::Constraint_Us:
- case InlineAsm::Constraint_Ut:
- case InlineAsm::Constraint_Uv:
- case InlineAsm::Constraint_Uy:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::ConstraintCode::Um:
+ case InlineAsm::ConstraintCode::Un:
+ case InlineAsm::ConstraintCode::Uq:
+ case InlineAsm::ConstraintCode::Us:
+ case InlineAsm::ConstraintCod...
|
|
@llvm/pr-subscribers-backend-m68k ChangesSimilar to Fix the TODOs added in -- Patch is 34.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66003.diff 25 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 557c6ef03d96b98..d3907865a659121 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -89,9 +89,10 @@ class SelectionDAGISel : public MachineFunctionPass {
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) {
+ virtual bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
return true;
}
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 12b280d5b1a0bcd..f4feab495932294 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4833,16 +4833,17 @@ class TargetLowering : public TargetLoweringBase {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const;
- virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+ virtual InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const {
if (ConstraintCode == "m")
- return InlineAsm::Constraint_m;
+ return InlineAsm::ConstraintCode::m;
if (ConstraintCode == "o")
- return InlineAsm::Constraint_o;
+ return InlineAsm::ConstraintCode::o;
if (ConstraintCode == "X")
- return InlineAsm::Constraint_X;
+ return InlineAsm::ConstraintCode::X;
if (ConstraintCode == "p")
- return InlineAsm::Constraint_p;
- return InlineAsm::Constraint_Unknown;
+ return InlineAsm::ConstraintCode::p;
+ return InlineAsm::ConstraintCode::Unknown;
}
/// Try to replace an X constraint, which matches anything, with another that
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index f73666fa8dc08e7..a4032ce7abde331 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -217,48 +217,6 @@ class InlineAsm final : public Value {
Extra_MayLoad = 8,
Extra_MayStore = 16,
Extra_IsConvergent = 32,
-
- // Memory constraint codes.
- // These could be tablegenerated but there's little need to do that since
- // there's plenty of space in the encoding to support the union of all
- // constraint codes for all targets.
- // Addresses are included here as they need to be treated the same by the
- // backend, the only difference is that they are not used to actaully
- // access memory by the instruction.
- // TODO: convert to enum?
- Constraint_Unknown = 0,
- Constraint_es,
- Constraint_i,
- Constraint_k,
- Constraint_m,
- Constraint_o,
- Constraint_v,
- Constraint_A,
- Constraint_Q,
- Constraint_R,
- Constraint_S,
- Constraint_T,
- Constraint_Um,
- Constraint_Un,
- Constraint_Uq,
- Constraint_Us,
- Constraint_Ut,
- Constraint_Uv,
- Constraint_Uy,
- Constraint_X,
- Constraint_Z,
- Constraint_ZB,
- Constraint_ZC,
- Constraint_Zy,
-
- // Address constraints
- Constraint_p,
- Constraint_ZQ,
- Constraint_ZR,
- Constraint_ZS,
- Constraint_ZT,
-
- Constraints_Max = Constraint_ZT,
};
// Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -274,6 +232,46 @@ class InlineAsm final : public Value {
Func = 7, // Address operand of function call
};
+ // Memory constraint codes.
+ // Addresses are included here as they need to be treated the same by the
+ // backend, the only difference is that they are not used to actaully
+ // access memory by the instruction.
+ enum class ConstraintCode : uint32_t {
+ Unknown = 0,
+ es,
+ i,
+ k,
+ m,
+ o,
+ v,
+ A,
+ Q,
+ R,
+ S,
+ T,
+ Um,
+ Un,
+ Uq,
+ Us,
+ Ut,
+ Uv,
+ Uy,
+ X,
+ Z,
+ ZB,
+ ZC,
+ Zy,
+
+ // Address constraints
+ p,
+ ZQ,
+ ZR,
+ ZS,
+ ZT,
+
+ Max = ZT,
+ };
+
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
//
@@ -375,11 +373,14 @@ class InlineAsm final : public Value {
return true;
}
- // TODO: convert to enum?
- unsigned getMemoryConstraintID() const {
+ ConstraintCode getMemoryConstraintID() const {
assert((isMemKind() || isFuncKind()) &&
"Not expected mem or function flag!");
- return getData();
+ uint32_t D = getData();
+ assert(D < static_cast(ConstraintCode::Max) &&
+ D >= static_cast(ConstraintCode::Unknown) &&
+ "unexpected value for memory constraint");
+ return static_cast(D);
}
/// setMatchingOp - Augment an existing flag with information indicating
@@ -403,12 +404,11 @@ class InlineAsm final : public Value {
/// setMemConstraint - Augment an existing flag with the constraint code for
/// a memory constraint.
- void setMemConstraint(unsigned Constraint) {
+ void setMemConstraint(ConstraintCode C) {
assert((isMemKind() || isFuncKind()) &&
"Flag is not a memory or function constraint!");
- assert(Constraint <= Constraints_Max && "Unknown constraint ID");
assert(getData() == 0 && "Mem constraint already set");
- setData(Constraint);
+ setData(static_cast(C));
}
/// clearMemConstraint - Similar to setMemConstraint(0), but without the
/// assertion checking that the constraint has not been set previously.
@@ -443,61 +443,61 @@ class InlineAsm final : public Value {
return Result;
}
- static StringRef getMemConstraintName(unsigned Constraint) {
- switch (Constraint) {
- case InlineAsm::Constraint_es:
+ static StringRef getMemConstraintName(const ConstraintCode C) {
+ switch (C) {
+ case ConstraintCode::es:
return "es";
- case InlineAsm::Constraint_i:
+ case ConstraintCode::i:
return "i";
- case InlineAsm::Constraint_k:
+ case ConstraintCode::k:
return "k";
- case InlineAsm::Constraint_m:
+ case ConstraintCode::m:
return "m";
- case InlineAsm::Constraint_o:
+ case ConstraintCode::o:
return "o";
- case InlineAsm::Constraint_v:
+ case ConstraintCode::v:
return "v";
- case InlineAsm::Constraint_Q:
+ case ConstraintCode::Q:
return "Q";
- case InlineAsm::Constraint_R:
+ case ConstraintCode::R:
return "R";
- case InlineAsm::Constraint_S:
+ case ConstraintCode::S:
return "S";
- case InlineAsm::Constraint_T:
+ case ConstraintCode::T:
return "T";
- case InlineAsm::Constraint_Um:
+ case ConstraintCode::Um:
return "Um";
- case InlineAsm::Constraint_Un:
+ case ConstraintCode::Un:
return "Un";
- case InlineAsm::Constraint_Uq:
+ case ConstraintCode::Uq:
return "Uq";
- case InlineAsm::Constraint_Us:
+ case ConstraintCode::Us:
return "Us";
- case InlineAsm::Constraint_Ut:
+ case ConstraintCode::Ut:
return "Ut";
- case InlineAsm::Constraint_Uv:
+ case ConstraintCode::Uv:
return "Uv";
- case InlineAsm::Constraint_Uy:
+ case ConstraintCode::Uy:
return "Uy";
- case InlineAsm::Constraint_X:
+ case ConstraintCode::X:
return "X";
- case InlineAsm::Constraint_Z:
+ case ConstraintCode::Z:
return "Z";
- case InlineAsm::Constraint_ZB:
+ case ConstraintCode::ZB:
return "ZB";
- case InlineAsm::Constraint_ZC:
+ case ConstraintCode::ZC:
return "ZC";
- case InlineAsm::Constraint_Zy:
+ case ConstraintCode::Zy:
return "Zy";
- case InlineAsm::Constraint_p:
+ case ConstraintCode::p:
return "p";
- case InlineAsm::Constraint_ZQ:
+ case ConstraintCode::ZQ:
return "ZQ";
- case InlineAsm::Constraint_ZR:
+ case ConstraintCode::ZR:
return "ZR";
- case InlineAsm::Constraint_ZS:
+ case ConstraintCode::ZS:
return "ZS";
- case InlineAsm::Constraint_ZT:
+ case ConstraintCode::ZT:
return "ZT";
default:
llvm_unreachable("Unknown memory constraint");
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 9944ba15997687a..00dba57fcb80227 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
OpFlags.setMemConstraint(ConstraintID);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 8cc3391e0d96a3d..d8467e2af8786ec 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 738dd10633db6a5..720fc4944161225 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
TLI.getPointerTy(DAG.getDataLayout()) &&
"Memory operands expect pointer values");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
}
if (OpInfo.ConstraintType == TargetLowering::C_Address) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a7873241df62e52..91b9d77eed70596 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2101,7 +2101,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector &Ops,
// Otherwise, this is a memory operand. Ask the target to select it.
std::vector SelOps;
- unsigned ConstraintID = Flags.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode ConstraintID =
+ Flags.getMemoryConstraintID();
if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
report_fatal_error("Could not match memory address. Inline asm"
" failure!");
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 686044ea572ac0d..bf1605f06bd88d6 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 60a155a86667e89..740995849740fef 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -61,9 +61,10 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
template
bool SelectRDVLImm(SDValue N, SDValue &Imm);
@@ -533,13 +534,14 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
#endif
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 67c344318e0d3ec..f2696b6b97593a1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1169,9 +1169,10 @@ class AArch64TargetLowering : public TargetLowering {
std::vector &Ops,
SelectionDAG &DAG) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
// followed by llvm_unreachable so we'll leave them unimplemented in
// the backend for now.
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 5f4fab0675824fd..9956b1b040b329d 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -331,8 +331,10 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) override;
// Form pairs of consecutive R, S, D, or Q registers.
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
@@ -5864,23 +5866,22 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
return true;
}
-
-bool ARMDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector &OutOps) {
+bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
- case InlineAsm::Constraint_Um:
- case InlineAsm::Constraint_Un:
- case InlineAsm::Constraint_Uq:
- case InlineAsm::Constraint_Us:
- case InlineAsm::Constraint_Ut:
- case InlineAsm::Constraint_Uv:
- case InlineAsm::Constraint_Uy:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::ConstraintCode::Um:
+ case InlineAsm::ConstraintCode::Un:
+ case InlineAsm::ConstraintCode::Uq:
+ case InlineAsm::ConstraintCode::Us:
+ case InlineAsm::ConstraintCod...
|
mshockwave
approved these changes
Sep 12, 2023
bwendling
reviewed
Sep 12, 2023
| @@ -2521,13 +2521,13 @@ AVRTargetLowering::getConstraintType(StringRef Constraint) const { | |||
| return TargetLowering::getConstraintType(Constraint); | |||
| } | |||
|
|
|||
| unsigned | |||
| InlineAsm::ConstraintCode | |||
| AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const { | |||
| // Not sure if this is actually the right thing to do, but we got to do | |||
| // *something* [agnat] | |||
| switch (ConstraintCode[0]) { | |||
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I know this is just a simple refactoring in this case, but could you turn this into an if-then statement instead? The switch seems unnecessary.
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Disagree. This causes much less churn if and when new cases need to be added.
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Sorry @bwendling , I agree with @jrtc27 . These kinds of memory-only constraints don't get added often, but I also doubt that LLVM supports all of https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html for all backend LLVM has. I forsee these changing, at least for the more modern and well supported architectures.
| switch (ConstraintID) { | ||
| case InlineAsm::Constraint_m: | ||
| case InlineAsm::ConstraintCode::m: |
| RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const { | ||
| // Currently only support length 1 constraints. | ||
| if (ConstraintCode.size() == 1) { | ||
| switch (ConstraintCode[0]) { | ||
| case 'A': | ||
| return InlineAsm::Constraint_A; | ||
| return InlineAsm::ConstraintCode::A; |
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What's up with the swtich statements? :)
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I don't have much standing for most other backends, but for RISC-V I will put a hard no on refactoring this.
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+1 Please don't refactor any targets, and especially not in a NFC commit
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@RKSimon well, this change is refactoring targets in an NFC commit. I assume you meant "please don't change this switch to an if-else chain" rather than "I reject this PR outright?"
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Yes - if somebody wants to replace switches with if-else then that should be in a followup patch. But even then, my preference would be to consistently keep to the switch pattern.
|
forced push to rebase on top of 94a7529. |
|
I believe this broke the AMDGPU OpenMP buildbot https://lab.llvm.org/buildbot/#/builders/193 |
|
No I resolved a merge commit wrong will fix. |
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|
fixed in 8b9bf3a |
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|
@rnk ah I thought I had removed I did, but rerunning This is the kind of thing I hate about cmake (and cmake's caches). cc @petrhosek Dunno if there's anything we can change in LLVM's usage of cmake to fix that, or if developers are simply expected to |
Sorry for crashing the thread, does unsetting the variable with |
You can also use |
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This reverts commit ee643b7. Fix up build failures I missed in llvm#66003
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|
attempt to reland: #66264 PTAL |
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I recently went to merge a PR that had a merge conflict:
$ gh pr merge --squash --delete-branch
X Pull request llvm#66003 is not mergeable: the merge commit cannot be cleanly created.
To have the pull request merged after all the requirements have been met, add the `--auto` flag.
Run the following to resolve the merge conflicts locally:
gh pr checkout 66003 && git fetch origin main && git merge origin/main
This is how I resolved it; we should recommend this explicitly for
fellow contributors.
nickdesaulniers
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Sep 13, 2023
reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66003) This reverts commit ee643b7. Fix up build failures in targets I missed in #66003 Kept as 3 commits for reviewers to see better what's changed. Will squash when merging. - reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66003) - fix all the targets I missed in #66003 - fix off by one found by llvm/test/CodeGen/SystemZ/inline-asm-addr.ll
|
My approach to managing cmake config options is to put them in a shell script ( |
+1, I do the same. In many cases, keeping the cache works, but rerunning cmake with an existing cache and omitting variables on the command line often will keep your last value, as opposed to what you'd get if running it in an empty directory. |
nickdesaulniers
added a commit
that referenced
this pull request
Sep 13, 2023
I recently went to merge a PR that had a merge conflict:
$ gh pr merge --squash --delete-branch
X Pull request #66003 is not mergeable: the merge commit cannot be
cleanly created.
To have the pull request merged after all the requirements have been
met, add the `--auto` flag.
Run the following to resolve the merge conflicts locally:
gh pr checkout 66003 && git fetch origin main && git merge origin/main
This is how I resolved it; we should recommend this explicitly for
fellow contributors.
Perhaps that's what I need. i.e. ALWAYS set Though that makes we wonder if there's a corresponding directive we can add to one of LLVM's CMakeLists.txt to force that? Perhaps that would have some unintended issue for folks that aren't swapping on+off various backends like I tend to do. I wonder if I removed |
ZijunZhaoCCK
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that referenced
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Sep 19, 2023
Similar to commit 2fad6e6 ("[InlineAsm] wrap Kind in enum class NFC") Fix the TODOs added in commit 93bd428 ("[InlineAsm] refactor InlineAsm class NFC (llvm#65649)")
ZijunZhaoCCK
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ZijunZhaoCCK
pushed a commit
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Sep 19, 2023
ZijunZhaoCCK
pushed a commit
to ZijunZhaoCCK/llvm-project
that referenced
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Sep 19, 2023
reland [InlineAsm] wrap ConstraintCode in enum class NFC (llvm#66003) This reverts commit ee643b7. Fix up build failures in targets I missed in llvm#66003 Kept as 3 commits for reviewers to see better what's changed. Will squash when merging. - reland [InlineAsm] wrap ConstraintCode in enum class NFC (llvm#66003) - fix all the targets I missed in llvm#66003 - fix off by one found by llvm/test/CodeGen/SystemZ/inline-asm-addr.ll
ZijunZhaoCCK
pushed a commit
to ZijunZhaoCCK/llvm-project
that referenced
this pull request
Sep 19, 2023
I recently went to merge a PR that had a merge conflict:
$ gh pr merge --squash --delete-branch
X Pull request llvm#66003 is not mergeable: the merge commit cannot be
cleanly created.
To have the pull request merged after all the requirements have been
met, add the `--auto` flag.
Run the following to resolve the merge conflicts locally:
gh pr checkout 66003 && git fetch origin main && git merge origin/main
This is how I resolved it; we should recommend this explicitly for
fellow contributors.
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Similar to
commit 2fad6e6 ("[InlineAsm] wrap Kind in enum class NFC")
Fix the TODOs added in
commit 93bd428 ("[InlineAsm] refactor InlineAsm class NFC (#65649)")