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[AMDGPU][NFC] Update GISel memory-legalizer-atomic-fence test #72829
Conversation
Test needs to be moved to MIR checks and use stop-after=si-memory-legalizer to avoid being optimized out in a future patch.
@llvm/pr-subscribers-llvm-globalisel Author: Pierre van Houtryve (Pierre-vh) ChangesTest needs to be moved to MIR checks and use stop-after=si-memory-legalizer to avoid being optimized out in a future patch. Patch is 66.63 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/72829.diff 1 Files Affected:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
index 0fbfe4cb6f35f13..601cc791c04141a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
@@ -1,720 +1,1510 @@
-; RUN: llc -global-isel -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX6,GFX68 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10WGP %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10CU %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10WGP %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+cumode -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10CU %s
-
-; FUNC-LABEL: {{^}}system_one_as_acquire:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GFX6: s_waitcnt vmcnt(0){{$}}
-; GFX6-NEXT: buffer_wbinvl1{{$}}
-; GFX8: s_waitcnt vmcnt(0){{$}}
-; GFX8-NEXT: buffer_wbinvl1_vol{{$}}
-; GFX10: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GFX10-NEXT: buffer_gl0_inv{{$}}
-; GFX10-NEXT: buffer_gl1_inv{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel system_one_as_acquire
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10WGP %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10CU %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11WGP %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+cumode -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11CU %s
+
+; Note: we use MIR test checks + stop after legalizer to prevent
+; tests from being optimized out.
+
define amdgpu_kernel void @system_one_as_acquire() {
+ ; GFX6-LABEL: name: system_one_as_acquire
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_WAITCNT 3952
+ ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: system_one_as_acquire
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_WAITCNT 3952
+ ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: system_one_as_acquire
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_WAITCNT 16240
+ ; GFX10WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: system_one_as_acquire
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_WAITCNT 16240
+ ; GFX10CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: system_one_as_acquire
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_WAITCNT 1015
+ ; GFX11WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: system_one_as_acquire
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_WAITCNT 1015
+ ; GFX11CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("one-as") acquire
ret void
}
-; FUNC-LABEL: {{^}}system_one_as_release:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel system_one_as_release
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_one_as_release() {
+ ; GFX6-LABEL: name: system_one_as_release
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_WAITCNT 3952
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: system_one_as_release
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_WAITCNT 3952
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: system_one_as_release
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_WAITCNT 16240
+ ; GFX10WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: system_one_as_release
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_WAITCNT 16240
+ ; GFX10CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: system_one_as_release
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_WAITCNT 1015
+ ; GFX11WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: system_one_as_release
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_WAITCNT 1015
+ ; GFX11CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("one-as") release
ret void
}
-; FUNC-LABEL: {{^}}system_one_as_acq_rel:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GFX6: buffer_wbinvl1{{$}}
-; GFX8: buffer_wbinvl1_vol{{$}}
-; GFX10-NEXT: buffer_gl0_inv{{$}}
-; GFX10-NEXT: buffer_gl1_inv{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel system_one_as_acq_rel
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_one_as_acq_rel() {
+ ; GFX6-LABEL: name: system_one_as_acq_rel
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_WAITCNT 3952
+ ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: system_one_as_acq_rel
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_WAITCNT 3952
+ ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: system_one_as_acq_rel
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_WAITCNT 16240
+ ; GFX10WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: system_one_as_acq_rel
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_WAITCNT 16240
+ ; GFX10CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: system_one_as_acq_rel
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_WAITCNT 1015
+ ; GFX11WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: system_one_as_acq_rel
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_WAITCNT 1015
+ ; GFX11CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("one-as") acq_rel
ret void
}
-; FUNC-LABEL: {{^}}system_one_as_seq_cst:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GFX6: buffer_wbinvl1{{$}}
-; GFX8: buffer_wbinvl1_vol{{$}}
-; GFX10-NEXT: buffer_gl0_inv{{$}}
-; GFX10-NEXT: buffer_gl1_inv{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel system_one_as_seq_cst
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_one_as_seq_cst() {
+ ; GFX6-LABEL: name: system_one_as_seq_cst
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_WAITCNT 3952
+ ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: system_one_as_seq_cst
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_WAITCNT 3952
+ ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: system_one_as_seq_cst
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_WAITCNT 16240
+ ; GFX10WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: system_one_as_seq_cst
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_WAITCNT 16240
+ ; GFX10CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: system_one_as_seq_cst
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_WAITCNT 1015
+ ; GFX11WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: system_one_as_seq_cst
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_WAITCNT 1015
+ ; GFX11CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("one-as") seq_cst
ret void
}
-; FUNC-LABEL: {{^}}singlethread_one_as_acquire:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel singlethread_one_as_acquire
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_one_as_acquire() {
+ ; GFX6-LABEL: name: singlethread_one_as_acquire
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: singlethread_one_as_acquire
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: singlethread_one_as_acquire
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: singlethread_one_as_acquire
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: singlethread_one_as_acquire
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: singlethread_one_as_acquire
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("singlethread-one-as") acquire
ret void
}
-; FUNC-LABEL: {{^}}singlethread_one_as_release:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel singlethread_one_as_release
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_one_as_release() {
+ ; GFX6-LABEL: name: singlethread_one_as_release
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: singlethread_one_as_release
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: singlethread_one_as_release
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: singlethread_one_as_release
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: singlethread_one_as_release
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: singlethread_one_as_release
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("singlethread-one-as") release
ret void
}
-; FUNC-LABEL: {{^}}singlethread_one_as_acq_rel:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel singlethread_one_as_acq_rel
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_one_as_acq_rel() {
+ ; GFX6-LABEL: name: singlethread_one_as_acq_rel
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: singlethread_one_as_acq_rel
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: singlethread_one_as_acq_rel
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: singlethread_one_as_acq_rel
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: singlethread_one_as_acq_rel
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: singlethread_one_as_acq_rel
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("singlethread-one-as") acq_rel
ret void
}
-; FUNC-LABEL: {{^}}singlethread_one_as_seq_cst:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel singlethread_one_as_seq_cst
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_one_as_seq_cst() {
+ ; GFX6-LABEL: name: singlethread_one_as_seq_cst
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: singlethread_one_as_seq_cst
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: singlethread_one_as_seq_cst
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: singlethread_one_as_seq_cst
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: singlethread_one_as_seq_cst
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: singlethread_one_as_seq_cst
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("singlethread-one-as") seq_cst
ret void
}
-; FUNC-LABEL: {{^}}agent_one_as_acquire:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GFX6: s_waitcnt vmcnt(0){{$}}
-; GFX6-NEXT: buffer_wbinvl1{{$}}
-; GFX8: s_waitcnt vmcnt(0){{$}}
-; GFX8-NEXT: buffer_wbinvl1_vol{{$}}
-; GFX10: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GFX10-NEXT: buffer_gl0_inv{{$}}
-; GFX10-NEXT: buffer_gl1_inv{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel agent_one_as_acquire
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_one_as_acquire() {
+ ; GFX6-LABEL: name: agent_one_as_acquire
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_WAITCNT 3952
+ ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: agent_one_as_acquire
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_WAITCNT 3952
+ ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: agent_one_as_acquire
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_WAITCNT 16240
+ ; GFX10WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: agent_one_as_acquire
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_WAITCNT 16240
+ ; GFX10CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: agent_one_as_acquire
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_WAITCNT 1015
+ ; GFX11WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: agent_one_as_acquire
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_WAITCNT 1015
+ ; GFX11CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("agent-one-as") acquire
ret void
}
-; FUNC-LABEL: {{^}}agent_one_as_release:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel agent_one_as_release
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_one_as_release() {
+ ; GFX6-LABEL: name: agent_one_as_release
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_WAITCNT 3952
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: agent_one_as_release
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_WAITCNT 3952
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: agent_one_as_release
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_WAITCNT 16240
+ ; GFX10WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: agent_one_as_release
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_WAITCNT 16240
+ ; GFX10CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: agent_one_as_release
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_WAITCNT 1015
+ ; GFX11WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: agent_one_as_release
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_WAITCNT 1015
+ ; GFX11CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("agent-one-as") release
ret void
}
-; FUNC-LABEL: {{^}}agent_one_as_acq_rel:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GFX6: buffer_wbinvl1{{$}}
-; GFX8: buffer_wbinvl1_vol{{$}}
-; GFX10-NEXT: buffer_gl0_inv{{$}}
-; GFX10-NEXT: buffer_gl1_inv{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel agent_one_as_acq_rel
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_one_as_acq_rel() {
+ ; GFX6-LABEL: name: agent_one_as_acq_rel
+ ; GFX6: bb...
[truncated]
|
@llvm/pr-subscribers-backend-amdgpu Author: Pierre van Houtryve (Pierre-vh) ChangesTest needs to be moved to MIR checks and use stop-after=si-memory-legalizer to avoid being optimized out in a future patch. Patch is 66.63 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/72829.diff 1 Files Affected:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
index 0fbfe4cb6f35f13..601cc791c04141a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
@@ -1,720 +1,1510 @@
-; RUN: llc -global-isel -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX6,GFX68 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10WGP %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10CU %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10WGP %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+cumode -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10CU %s
-
-; FUNC-LABEL: {{^}}system_one_as_acquire:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GFX6: s_waitcnt vmcnt(0){{$}}
-; GFX6-NEXT: buffer_wbinvl1{{$}}
-; GFX8: s_waitcnt vmcnt(0){{$}}
-; GFX8-NEXT: buffer_wbinvl1_vol{{$}}
-; GFX10: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GFX10-NEXT: buffer_gl0_inv{{$}}
-; GFX10-NEXT: buffer_gl1_inv{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel system_one_as_acquire
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10WGP %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10CU %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11WGP %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+cumode -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11CU %s
+
+; Note: we use MIR test checks + stop after legalizer to prevent
+; tests from being optimized out.
+
define amdgpu_kernel void @system_one_as_acquire() {
+ ; GFX6-LABEL: name: system_one_as_acquire
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_WAITCNT 3952
+ ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: system_one_as_acquire
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_WAITCNT 3952
+ ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: system_one_as_acquire
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_WAITCNT 16240
+ ; GFX10WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: system_one_as_acquire
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_WAITCNT 16240
+ ; GFX10CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: system_one_as_acquire
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_WAITCNT 1015
+ ; GFX11WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: system_one_as_acquire
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_WAITCNT 1015
+ ; GFX11CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("one-as") acquire
ret void
}
-; FUNC-LABEL: {{^}}system_one_as_release:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel system_one_as_release
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_one_as_release() {
+ ; GFX6-LABEL: name: system_one_as_release
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_WAITCNT 3952
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: system_one_as_release
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_WAITCNT 3952
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: system_one_as_release
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_WAITCNT 16240
+ ; GFX10WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: system_one_as_release
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_WAITCNT 16240
+ ; GFX10CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: system_one_as_release
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_WAITCNT 1015
+ ; GFX11WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: system_one_as_release
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_WAITCNT 1015
+ ; GFX11CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("one-as") release
ret void
}
-; FUNC-LABEL: {{^}}system_one_as_acq_rel:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GFX6: buffer_wbinvl1{{$}}
-; GFX8: buffer_wbinvl1_vol{{$}}
-; GFX10-NEXT: buffer_gl0_inv{{$}}
-; GFX10-NEXT: buffer_gl1_inv{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel system_one_as_acq_rel
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_one_as_acq_rel() {
+ ; GFX6-LABEL: name: system_one_as_acq_rel
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_WAITCNT 3952
+ ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: system_one_as_acq_rel
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_WAITCNT 3952
+ ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: system_one_as_acq_rel
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_WAITCNT 16240
+ ; GFX10WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: system_one_as_acq_rel
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_WAITCNT 16240
+ ; GFX10CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: system_one_as_acq_rel
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_WAITCNT 1015
+ ; GFX11WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: system_one_as_acq_rel
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_WAITCNT 1015
+ ; GFX11CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("one-as") acq_rel
ret void
}
-; FUNC-LABEL: {{^}}system_one_as_seq_cst:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GFX6: buffer_wbinvl1{{$}}
-; GFX8: buffer_wbinvl1_vol{{$}}
-; GFX10-NEXT: buffer_gl0_inv{{$}}
-; GFX10-NEXT: buffer_gl1_inv{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel system_one_as_seq_cst
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @system_one_as_seq_cst() {
+ ; GFX6-LABEL: name: system_one_as_seq_cst
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_WAITCNT 3952
+ ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: system_one_as_seq_cst
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_WAITCNT 3952
+ ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: system_one_as_seq_cst
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_WAITCNT 16240
+ ; GFX10WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: system_one_as_seq_cst
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_WAITCNT 16240
+ ; GFX10CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: system_one_as_seq_cst
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_WAITCNT 1015
+ ; GFX11WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: system_one_as_seq_cst
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_WAITCNT 1015
+ ; GFX11CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("one-as") seq_cst
ret void
}
-; FUNC-LABEL: {{^}}singlethread_one_as_acquire:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel singlethread_one_as_acquire
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_one_as_acquire() {
+ ; GFX6-LABEL: name: singlethread_one_as_acquire
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: singlethread_one_as_acquire
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: singlethread_one_as_acquire
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: singlethread_one_as_acquire
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: singlethread_one_as_acquire
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: singlethread_one_as_acquire
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("singlethread-one-as") acquire
ret void
}
-; FUNC-LABEL: {{^}}singlethread_one_as_release:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel singlethread_one_as_release
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_one_as_release() {
+ ; GFX6-LABEL: name: singlethread_one_as_release
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: singlethread_one_as_release
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: singlethread_one_as_release
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: singlethread_one_as_release
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: singlethread_one_as_release
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: singlethread_one_as_release
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("singlethread-one-as") release
ret void
}
-; FUNC-LABEL: {{^}}singlethread_one_as_acq_rel:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel singlethread_one_as_acq_rel
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_one_as_acq_rel() {
+ ; GFX6-LABEL: name: singlethread_one_as_acq_rel
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: singlethread_one_as_acq_rel
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: singlethread_one_as_acq_rel
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: singlethread_one_as_acq_rel
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: singlethread_one_as_acq_rel
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: singlethread_one_as_acq_rel
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("singlethread-one-as") acq_rel
ret void
}
-; FUNC-LABEL: {{^}}singlethread_one_as_seq_cst:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel singlethread_one_as_seq_cst
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @singlethread_one_as_seq_cst() {
+ ; GFX6-LABEL: name: singlethread_one_as_seq_cst
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: singlethread_one_as_seq_cst
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: singlethread_one_as_seq_cst
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: singlethread_one_as_seq_cst
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: singlethread_one_as_seq_cst
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: singlethread_one_as_seq_cst
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("singlethread-one-as") seq_cst
ret void
}
-; FUNC-LABEL: {{^}}agent_one_as_acquire:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GFX6: s_waitcnt vmcnt(0){{$}}
-; GFX6-NEXT: buffer_wbinvl1{{$}}
-; GFX8: s_waitcnt vmcnt(0){{$}}
-; GFX8-NEXT: buffer_wbinvl1_vol{{$}}
-; GFX10: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GFX10-NEXT: buffer_gl0_inv{{$}}
-; GFX10-NEXT: buffer_gl1_inv{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel agent_one_as_acquire
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_one_as_acquire() {
+ ; GFX6-LABEL: name: agent_one_as_acquire
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_WAITCNT 3952
+ ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: agent_one_as_acquire
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_WAITCNT 3952
+ ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: agent_one_as_acquire
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_WAITCNT 16240
+ ; GFX10WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: agent_one_as_acquire
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_WAITCNT 16240
+ ; GFX10CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: agent_one_as_acquire
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_WAITCNT 1015
+ ; GFX11WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: agent_one_as_acquire
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_WAITCNT 1015
+ ; GFX11CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11CU-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("agent-one-as") acquire
ret void
}
-; FUNC-LABEL: {{^}}agent_one_as_release:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel agent_one_as_release
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_one_as_release() {
+ ; GFX6-LABEL: name: agent_one_as_release
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_WAITCNT 3952
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: agent_one_as_release
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_WAITCNT 3952
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: agent_one_as_release
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_WAITCNT 16240
+ ; GFX10WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: agent_one_as_release
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_WAITCNT 16240
+ ; GFX10CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10CU-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11WGP-LABEL: name: agent_one_as_release
+ ; GFX11WGP: bb.0.entry:
+ ; GFX11WGP-NEXT: S_WAITCNT 1015
+ ; GFX11WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX11CU-LABEL: name: agent_one_as_release
+ ; GFX11CU: bb.0.entry:
+ ; GFX11CU-NEXT: S_WAITCNT 1015
+ ; GFX11CU-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX11CU-NEXT: S_ENDPGM 0
entry:
fence syncscope("agent-one-as") release
ret void
}
-; FUNC-LABEL: {{^}}agent_one_as_acq_rel:
-; GCN: %bb.0
-; GCN-NOT: ATOMIC_FENCE
-; GCN: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GFX6: buffer_wbinvl1{{$}}
-; GFX8: buffer_wbinvl1_vol{{$}}
-; GFX10-NEXT: buffer_gl0_inv{{$}}
-; GFX10-NEXT: buffer_gl1_inv{{$}}
-; GCN: s_endpgm
-; GFX10: .amdhsa_kernel agent_one_as_acq_rel
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @agent_one_as_acq_rel() {
+ ; GFX6-LABEL: name: agent_one_as_acq_rel
+ ; GFX6: bb...
[truncated]
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LGTM
Test needs to be moved to MIR checks and use stop-after=si-memory-legalizer to avoid being optimized out in a future patch.