[CodeGen] This patch fix a bug that may caused error for a self-defined target in SelectionDAG::getNode

[zhou3968322]

we need first judge N1.getNumOperands() > 0.

If Lowering Generated SDNode like.

v2i32 t20:  TargetOpNode.
i32 t21: extract_vector_elt t20  0
i32 t22: extract_vector_elt t20 1

will cause a error.

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[llvmbot]

@llvm/pr-subscribers-llvm-selectiondag

Author: yan zhou (zhou3968322)

Changes

we need first judge N1.getNumOperands() > 0.

If Lowering Generated SDNode like.

v2i32 t20:  TargetOpNode.
i32 t21: extract_vector_elt t20  0
i32 t22: extract_vector_elt t20 1

will cause a error.

---

Full diff: https://github.com/llvm/llvm-project/pull/75320.diff

1 Files Affected:

• (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+3-2)

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 5be1892a44f6dd..5720d001d2e337 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6858,8 +6858,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     // expanding copies of large vectors from registers. This only works for
     // fixed length vectors, since we need to know the exact number of
     // elements.
-    if (N2C && N1.getOperand(0).getValueType().isFixedLengthVector() &&
-        N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0) {
+    if (N2C && N1.getNumOperands() > 0 && 
+        N1.getOperand(0).getValueType().isFixedLengthVector() &&
+        N1.getOpcode() == ISD::CONCAT_VECTORS) {
       unsigned Factor =
         N1.getOperand(0).getValueType().getVectorNumElements();
       return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[RKSimon]

This looks OK by inspection, but do you have a test case you could add as well?

[zhou3968322]

This looks OK by inspection, but do you have a test case you could add as well?

No, for current targets, there is no dag SDNode like this:

t20 v2i32: TargetOpNode 

It only generated a v2i32 with no input operands.
while my self-defined target still has a lot of bugs, too early to give it's example.

But I think this is only an internal change and does not affect other modules.
It can help others want to define instr like this in td,may be proper to change.

[RKSimon]

LGTM - cheers

[zhou3968322]

@arsenm , no commit access, can you commit it on my behalf?

[vitalybuka]

I guess this is broken by this patch https://lab.llvm.org/buildbot/#/builders/238/builds/7108

[topperc]

I guess this is broken by this patch https://lab.llvm.org/buildbot/#/builders/238/builds/7108

Why do you suspect this patch?

[vitalybuka]

I guess this is broken by this patch https://lab.llvm.org/buildbot/#/builders/238/builds/7108

Why do you suspect this patch?

No PPC related patches
and the next in the stack is SelectionDAGBuilder
this patch is the only one related to SelectionDAG

[vitalybuka]

I guess this is broken by this patch https://lab.llvm.org/buildbot/#/builders/238/builds/7108

Why do you suspect this patch?

No PPC related patches and the next in the stack is SelectionDAGBuilder this patch is the only one related to SelectionDAG

That was my guess, and it was wrong. Local bisect shows f568763