[RISCV] Add sifive-p450 CPU.

[topperc]

This is an out of order core with no vector unit. More information: https://www.sifive.com/cores/performance-p450-470

Scheduler model and other tuning will come in separate patches.

[llvmbot]

@llvm/pr-subscribers-clang-driver
@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-clang

Author: Craig Topper (topperc)

Changes

This is an out of order core with no vector unit. More information: https://www.sifive.com/cores/performance-p450-470

Scheduler model and other tuning will come in separate patches.

---

Full diff: https://github.com/llvm/llvm-project/pull/75760.diff

2 Files Affected:

• (modified) clang/test/Misc/target-invalid-cpu-note.c (+2-2)
• (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+19)

diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index e840a9208f5a45..48e9f05d9b03de 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 58989fd716fa0e..16c79519fcacc1 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -216,6 +216,25 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
                                       [TuneSiFive7,
                                        TuneDLenFactor2]>;
 
+def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel,
+                                      [Feature64Bit,
+                                       FeatureStdExtZifencei,
+                                       FeatureStdExtM,
+                                       FeatureStdExtA,
+                                       FeatureStdExtF,
+                                       FeatureStdExtD,
+                                       FeatureStdExtC,
+                                       FeatureStdExtZicbop,
+                                       FeatureStdExtZicbom,
+                                       FeatureStdExtZicboz,
+                                       FeatureStdExtZihintntl,
+                                       FeatureStdExtZihintpause,
+                                       FeatureStdExtZihpm,
+                                       FeatureStdExtZba,
+                                       FeatureStdExtZbb,
+                                       FeatureStdExtZbs,
+                                       FeatureStdExtZfhmin]>;
+
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
                                               SyntacoreSCR1Model,
                                               [Feature32Bit,

[wangpc-pp]

Add test in clang/test/Driver/riscv-cpus.c?

[wangpc-pp]

Are there any experimental extensions?

[wangpc-pp]

Why does this line end with "-? Copy/paste mistake?
And this line is too long, please add some line breaks.

[topperc]

The "- is to make sure we check every positive feature. There are only negative features from there on.

I don't know how to add line breaks while making sure there are no target-features in the output that aren't being checked. The -SAME checks used on other CPUs allow things to be missed. For example SIFIVE-X280 should have +zfhmin after the recent change to make Zfh imply Zfhmin, but it's not caught because it occurs in the gap between the line that ends in +zfh and the next line.

I'm open to other suggestions for how to do this.

[wangpc-pp]

I prefer to the form of veyron-v1 test that there is exactly one line for one feature. We can just test features specified in RISCVProcessorModel definitions in RISCVProcessors.td. As for implied features, we can ignore them as there are test coverage in other tests and this is not the purpose of riscv-cpus.c I think.

[wangpc-pp]

I don't find the supported ISA description in datasheet, so I wonder if it's true that only Zfhmin is implemented. Should it be Zfh?

[topperc]

Zfhmin is correct. Its the minimum required for RVA22/RVA23 profiles.

[wangpc-pp]

LGTM.