[RISCV] Add support for Smepmp 1.0 #78489

mshockwave · 2024-01-17T19:15:17Z

Smepmp is a supervisor extension that prevents privileged processes from accessing unprivileged program and data.

https://github.com/riscv/riscv-tee/blob/main/Smepmp/Smepmp.pdf

llvmbot · 2024-01-17T19:15:48Z

@llvm/pr-subscribers-clang
@llvm/pr-subscribers-llvm-support
@llvm/pr-subscribers-mc

@llvm/pr-subscribers-backend-risc-v

Author: Min-Yih Hsu (mshockwave)

Changes

Smepmp is a supervisor extension that prevents privileged processes from accessing unprivileged program and data.

https://github.com/riscv/riscv-tee/blob/main/Smepmp/Smepmp.pdf

Full diff: https://github.com/llvm/llvm-project/pull/78489.diff

5 Files Affected:

(modified) llvm/lib/Support/RISCVISAInfo.cpp (+1)
(modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+7)
(modified) llvm/test/CodeGen/RISCV/attributes.ll (+4)
(modified) llvm/test/MC/RISCV/attribute-arch.s (+3)
(modified) llvm/unittests/Support/RISCVISAInfoTest.cpp (+1)

diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 390d950486a7956..f67bbd1969e1b37 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -55,6 +55,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
     {"m", {2, 0}},
 
     {"smaia", {1, 0}},
+    {"smepmp", {1, 0}},
     {"ssaia", {1, 0}},
     {"svinval", {1, 0}},
     {"svnapot", {1, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 279509575bb52a9..00b5c710daac322 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -716,6 +716,13 @@ def FeatureStdExtSmaia
                        "AIA specifies for a hart, over all privilege levels.)",
                        []>;
 
+def FeatureStdExtSmepmp
+    : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
+                       "'Smepmp' (Smepmp prevents privileged processes from "
+                       "executing or accessing unprivileged programs and"
+                       "data.)",
+                       []>;
+
 def FeatureStdExtSsaia
     : SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
                        "'Ssaia' (Ssaia is essentially the same as Smaia except "
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 9a6e78c09ad8c3f..ad6f205692fe30e 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -88,6 +88,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
+; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
@@ -182,6 +183,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
+; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
@@ -278,6 +280,7 @@
 ; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop0p1"
 ; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2"
 ; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
+; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
 ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
 ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8"
 ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
@@ -371,6 +374,7 @@
 ; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop0p1"
 ; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2"
 ; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
+; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
 ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
 ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8"
 ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 4f8a8dfdbcec903..bab104c5809008f 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -270,6 +270,9 @@
 .attribute arch, "rv32i_smaia1p0"
 # CHECK: attribute      5, "rv32i2p1_smaia1p0"
 
+.attribute arch, "rv32i_smepmp1p0"
+# CHECK: attribute      5, "rv32i2p1_smepmp1p0"
+
 .attribute arch, "rv32i_ssaia1p0"
 # CHECK: attribute      5, "rv32i2p1_ssaia1p0"
 
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 997551e5c44c092..fc96ea5ff3669ae 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -753,6 +753,7 @@ R"(All available -march extensions for RISC-V
     zhinx               1.0
     zhinxmin            1.0
     smaia               1.0
+    smepmp              1.0
     ssaia               1.0
     svinval             1.0
     svnapot             1.0

preames

Needs to be added to RISCVUsage.rst, and probably a note in the release docs as well.

topperc · 2024-01-17T20:40:36Z

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -716,6 +716,13 @@ def FeatureStdExtSmaia
                       "AIA specifies for a hart, over all privilege levels.)",
                       []>;

+def FeatureStdExtSmepmp


Can we keep smaia and ssaia together since they come from the same specification? I assume you were alphabetizing, but I don't think there's any order in this file.

Can we keep smaia and ssaia together since they come from the same specification? I assume you were alphabetizing, but I don't think there's any order in this file.

I've reordered it here and other places for consistency.

mshockwave · 2024-01-17T21:56:02Z

Needs to be added to RISCVUsage.rst, and probably a note in the release docs as well.

It's done now.

topperc · 2024-01-17T21:58:16Z

llvm/docs/RISCVUsage.rst

@@ -92,6 +92,7 @@ on support follow.
     ``M``            Supported
     ``Smaia``        Supported
     ``Ssaia``        Supported
+     ``Smepmp``       Supported


I think this list is aphabetized.

topperc · 2024-01-17T21:58:56Z

llvm/lib/Support/RISCVISAInfo.cpp

@@ -56,6 +56,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {

    {"smaia", {1, 0}},
    {"ssaia", {1, 0}},
+    {"smepmp", {1, 0}},


This is required to be alphabetized. It won't pass lit tests if it isn't. Might even fail when tablegen runs.

jrtc27 · 2024-01-18T00:42:04Z

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -722,6 +722,11 @@ def FeatureStdExtSsaia
                       "'Ssaia' (Advanced Interrupt Architecture Supervisor "
                       "Level)", []>;

+def FeatureStdExtSmepmp
+    : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
+                       "'Smepmp' (PMP Enhancements for memory access and "


This seems pretty clunky, what's wrong with just "Enhanced PMP" / "Enhanced Physical Memory Protection"? That's what it stands for after all...

It's fixed now.

topperc · 2024-01-18T21:14:54Z

clang/test/Preprocessor/riscv-target-features.c

+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32ismepmp1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \


This extension shouldn't require -menable-experimental-extensions

It's fixed now.

topperc · 2024-01-18T21:15:34Z

clang/test/Preprocessor/riscv-target-features.c

@@ -116,6 +116,7 @@

 // CHECK-NOT: __riscv_smaia {{.*$}}
 // CHECK-NOT: __riscv_ssaia {{.*$}}
+// CHECK-NOT: __riscv_smepmp {{.*$}}


This is the experimental extension section according to the comment on 115. I guess we're bad at moving things out of this section when they go non-experimental

It's fixed now.

Smepmp is a supervisor extension that prevents privileged processes from accessing unprivileged program and data.

topperc

LGTM

mshockwave requested review from topperc and yetingk January 17, 2024 19:15

llvmbot added backend:RISC-V mc Machine (object) code llvm:support labels Jan 17, 2024

mshockwave requested a review from kito-cheng January 17, 2024 19:16

topperc requested review from asb, preames and wangpc-pp January 17, 2024 20:36

preames reviewed Jan 17, 2024

View reviewed changes

topperc reviewed Jan 17, 2024

View reviewed changes

llvmbot added the clang Clang issues not falling into any other category label Jan 17, 2024

topperc reviewed Jan 17, 2024

View reviewed changes

mshockwave force-pushed the patch/riscv-smepmp branch from def71b1 to bb2e208 Compare January 17, 2024 22:19

jrtc27 reviewed Jan 18, 2024

View reviewed changes

mshockwave force-pushed the patch/riscv-smepmp branch from df49f8c to a05871b Compare January 18, 2024 19:28

topperc reviewed Jan 18, 2024

View reviewed changes

mshockwave added 4 commits January 19, 2024 09:53

[RISCV] Add support for Smepmp 1.0

ab316ea

Smepmp is a supervisor extension that prevents privileged processes from accessing unprivileged program and data.

fixup! [RISCV] Add support for Smepmp 1.0

5191469

Shorten the description in RISCVFeatures.td

36fd5f4

Smepmp shouldn't be experimental

fd3ee24

mshockwave force-pushed the patch/riscv-smepmp branch from a05871b to fd3ee24 Compare January 19, 2024 18:01

topperc approved these changes Jan 19, 2024

View reviewed changes

mshockwave merged commit 5330daa into llvm:main Jan 19, 2024
4 of 5 checks passed

mshockwave deleted the patch/riscv-smepmp branch January 19, 2024 19:09

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[RISCV] Add support for Smepmp 1.0 #78489

[RISCV] Add support for Smepmp 1.0 #78489

mshockwave commented Jan 17, 2024

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[RISCV] Add support for Smepmp 1.0 #78489

[RISCV] Add support for Smepmp 1.0 #78489

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