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[RISCV] Add support for Smepmp 1.0 #78489

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merged 4 commits into from
Jan 19, 2024
Merged

[RISCV] Add support for Smepmp 1.0 #78489

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ab316ea
[RISCV] Add support for Smepmp 1.0
mshockwave Jan 17, 2024
5191469
fixup! [RISCV] Add support for Smepmp 1.0
mshockwave Jan 17, 2024
36fd5f4
Shorten the description in RISCVFeatures.td
mshockwave Jan 18, 2024
fd3ee24
Smepmp shouldn't be experimental
mshockwave Jan 19, 2024
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9 changes: 9 additions & 0 deletions clang/test/Preprocessor/riscv-target-features.c
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Expand Up @@ -21,6 +21,7 @@
// CHECK-NOT: __riscv_muldiv {{.*$}}
// CHECK-NOT: __riscv_smaia {{.*$}}
// CHECK-NOT: __riscv_ssaia {{.*$}}
// CHECK-NOT: __riscv_smepmp {{.*$}}
// CHECK-NOT: __riscv_svinval {{.*$}}
// CHECK-NOT: __riscv_svnapot {{.*$}}
// CHECK-NOT: __riscv_svpbmt {{.*$}}
Expand Down Expand Up @@ -1108,6 +1109,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
// CHECK-SSAIA-EXT: __riscv_ssaia 1000000{{$}}

// RUN: %clang --target=riscv32 \
// RUN: -march=rv32ismepmp1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64ismepmp1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s
// CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}}

// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izfa -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
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1 change: 1 addition & 0 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -92,6 +92,7 @@ on support follow.
``H`` Assembly Support
``M`` Supported
``Smaia`` Supported
``Smepmp`` Supported
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I think this list is aphabetized.

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Done.

``Ssaia`` Supported
``Svinval`` Assembly Support
``Svnapot`` Assembly Support
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1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.rst
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Expand Up @@ -160,6 +160,7 @@ Changes to the RISC-V Backend
* Support was added for the Ziccif, Ziccrse, Ziccamoa, Zicclsm, Za64rs, Za128rs
and Zic64b extensions which were introduced as a part of the RISC-V Profiles
specification.
* The Smepmp 1.0 extension is now supported.

Changes to the WebAssembly Backend
----------------------------------
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1 change: 1 addition & 0 deletions llvm/lib/Support/RISCVISAInfo.cpp
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Expand Up @@ -55,6 +55,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"m", {2, 0}},

{"smaia", {1, 0}},
{"smepmp", {1, 0}},
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This is required to be alphabetized. It won't pass lit tests if it isn't. Might even fail when tablegen runs.

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Done.

{"ssaia", {1, 0}},
{"svinval", {1, 0}},
{"svnapot", {1, 0}},
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4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -748,6 +748,10 @@ def FeatureStdExtSsaia
"'Ssaia' (Advanced Interrupt Architecture Supervisor "
"Level)", []>;

def FeatureStdExtSmepmp
: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
"'Smepmp' (Enhanced Physical Memory Protection)", []>;

def HasHalfFPLoadStoreMove
: Predicate<"Subtarget->hasHalfFPLoadStoreMove()">,
AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin,
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4 changes: 4 additions & 0 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -89,6 +89,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
Expand Down Expand Up @@ -190,6 +191,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
Expand Down Expand Up @@ -286,6 +288,7 @@
; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
Expand Down Expand Up @@ -386,6 +389,7 @@
; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2"
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
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3 changes: 3 additions & 0 deletions llvm/test/MC/RISCV/attribute-arch.s
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Expand Up @@ -294,6 +294,9 @@
.attribute arch, "rv32i_ssaia1p0"
# CHECK: attribute 5, "rv32i2p1_ssaia1p0"

.attribute arch, "rv32i_smepmp1p0"
# CHECK: attribute 5, "rv32i2p1_smepmp1p0"

.attribute arch, "rv32i_zfbfmin1p0"
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"

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1 change: 1 addition & 0 deletions llvm/unittests/Support/RISCVISAInfoTest.cpp
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Expand Up @@ -760,6 +760,7 @@ R"(All available -march extensions for RISC-V
zhinx 1.0
zhinxmin 1.0
smaia 1.0
smepmp 1.0
ssaia 1.0
svinval 1.0
svnapot 1.0
Expand Down