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[AMDGPU] Rework architected SGPRs implementation #79001

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[AMDGPU] Rework architected SGPRs implementation #79001

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jayfoad
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@jayfoad jayfoad commented Jan 22, 2024

Rework the architected SGPRs implementation such that workgroup id
values (which live in TTMP registers) are available in all functions and
do not rely on calling allocateSystemSGPRs to set them up.

Rework the architected SGPRs implementation such that workgroup id
values (which live in TTMP registers) are available in all functions and
do not rely on calling allocateSystemSGPRs to set them up.
if (!AMDGPU::isGraphics(CC) ||
(CC == CallingConv::AMDGPU_CS && ST.hasArchitectedSGPRs())) {
if (!AMDGPU::isGraphics(CC) || CC == CallingConv::AMDGPU_CS ||
ST.hasArchitectedSGPRs()) {
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This change looks redundant as this patch always allocate the TTMP* for subtargets with architectedSGPR enabled.
This was initially added with 2171f04.
You can revert this check to just have only !AMDGPU::isGraphics(CC)

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But I need WorkGroupIDZ to be set correctly when architected SGPRs are enabled. It is used below, line 177.

; GCN: s_mov_b64 s[4:5], s[0:1]
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], 0 offset:4
; GCN: s_mov_b64 s[8:9], s[0:1]
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[8:11], 0 offset:4
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Is this expected?

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No, I guess I've broken something.

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The following change? It now enables workgroup IDs for AMDGPU_CS always.
SIMachineFunctionInfo.cpp:110

  • if (!AMDGPU::isGraphics(CC) ||
  • (CC == CallingConv::AMDGPU_CS && ST.hasArchitectedSGPRs())) {
  • if (!AMDGPU::isGraphics(CC) || CC == CallingConv::AMDGPU_CS ||
  • ST.hasArchitectedSGPRs()) {

@cdevadas
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The WaveID support is missing. Hope that will be coming in a separate patch.

@@ -143,6 +143,11 @@ struct AMDGPUFunctionArgInfo {
ArgDescriptor WorkGroupInfo;
ArgDescriptor PrivateSegmentWaveByteOffset;

// System TTMPs.
ArgDescriptor ArchitectedWorkGroupIDX;
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I don't think these really need to be tracked in ArgumentUsageInfo; they aren't arguments anymore

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OK. I started again from scratch: #79120

@@ -169,6 +169,15 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,
VGPRForAGPRCopy =
AMDGPU::VGPR_32RegClass.getRegister(ST.getMaxNumVGPRs(F) - 1);
}

if (STI->hasArchitectedSGPRs()) {
ArgInfo.ArchitectedWorkGroupIDX =
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I think it's OK for the lowering to directly consume the hardcoded register numbers

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You mean not go via these ArgDescriptors? I'm only using them because they handle the shifting and masking.

@jayfoad jayfoad closed this Jan 23, 2024
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3 participants