Promote the Pseudo Opcode of instructions that deduce the sign extension for extsw from 32 bits to 64 bits when eliminating the extsw instruction in PPCMIPeepholes optimization.

llvm/lib/Target/PowerPC/P10InstrResources.td

@@ -825,15 +825,17 @@ def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read],
 def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read],
       (instrs
     SRADI_rec,
-    SRAWI_rec
+    SRAWI_rec,
+    SRAWI8_rec
 )>;
 
 // Single crack instructions
 // 4 Cycles ALU2 operations, 2 input operands
 def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read, P10F2_Read],
       (instrs
     SRAD_rec,
-    SRAW_rec
+    SRAW_rec,
+    SRAW8_rec
 )>;
 
 // 2-way crack instructions
@@ -926,7 +928,7 @@ def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read],
     SETNBC, SETNBC8,
     SETNBCR, SETNBCR8,
     SRADI, SRADI_32,
-    SRAWI,
+    SRAWI, SRAWI8,
     SUBFIC, SUBFIC8,
     SUBFME, SUBFME8,
     SUBFME8O, SUBFMEO,
@@ -1008,7 +1010,7 @@ def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read],
     SLD,
     SLW, SLW8,
     SRAD,
-    SRAW,
+    SRAW, SRAW8,
     SRD,
     SRW, SRW8,
     SUBF, SUBF8,

llvm/lib/Target/PowerPC/P9InstrResources.td

@@ -189,7 +189,8 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_3SLOTS_1C],
     (instregex "F(N)?ABS(D|S)$"),
     (instregex "FNEG(D|S)$"),
     (instregex "FCPSGN(D|S)$"),
-    (instregex "SRAW(I)?$"),
+    (instregex "SRAW(8)?$"),
+    (instregex "SRAWI(8)?$"),
     (instregex "ISEL(8)?$"),
     RLDIMI,
     XSIEXPDP,
@@ -1091,7 +1092,8 @@ def : InstRW<[P9_ALUOpAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C,
     (instregex "RLD(I)?C(R|L)_rec$"),
     (instregex "RLW(IMI|INM|NM)(8)?_rec$"),
     (instregex "SLW(8)?_rec$"),
-    (instregex "SRAW(I)?_rec$"),
+    (instregex "SRAW(8)?_rec$"),
+    (instregex "SRAWI(8)?_rec$"),
     (instregex "SRW(8)?_rec$"),
     RLDICL_32_rec,
     RLDIMI_rec

llvm/lib/Target/PowerPC/PPC.td

@@ -534,6 +534,18 @@ def getAltVSXFMAOpcode : InstrMapping {
   let ValueCols = [["1"]];
 }
 
+def get64BitInstrFromSignedExt32BitInstr : InstrMapping {
+  let FilterClass = "SExt32To64";
+  // Instructions with the same opcode.
+  let RowFields = ["Inst"];
+  // Instructions with the same Interpretation64Bit value form a column.
+  let ColFields = ["Interpretation64Bit"];
+  // The key column are not the Interpretation64Bit-form instructions.
+  let KeyCol = ["0"];
+  // Value columns are the Interpretation64Bit-form instructions.
+  let ValueCols = [["1"]];
+}
+
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

@@ -932,6 +932,14 @@ defm SLW8  : XForm_6r<31,  24, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
                       "slw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64;
 defm SRW8  : XForm_6r<31, 536, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
                       "srw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64;
+
+defm SRAW8 : XForm_6rc<31, 792, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
+                      "sraw", "$RA, $RST, $RB", IIC_IntShift,
+                      [(set i64:$RA, (PPCsra i64:$RST, i64:$RB))]>, SExt32To64;
+
+defm SRAWI8 : XForm_10rc<31, 824, (outs g8rc:$RA), (ins g8rc:$RST, u5imm:$RB),
+            "srawi", "$RA, $RST, $RB", IIC_IntShift, []>, SExt32To64;
+
 } // Interpretation64Bit
 
 // For fast-isel:

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

@@ -5234,6 +5234,218 @@ bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const {
 // We limit the max depth to track incoming values of PHIs or binary ops
 // (e.g. AND) to avoid excessive cost.
 const unsigned MAX_BINOP_DEPTH = 1;
+
+void PPCInstrInfo::replaceInstrAfterElimExt32To64(const Register &Reg,
+                                                  MachineRegisterInfo *MRI,
+                                                  unsigned BinOpDepth,
+                                                  LiveVariables *LV) const {
+  MachineInstr *MI = MRI->getVRegDef(Reg);
+  if (!MI)
+    return;
+
+  unsigned Opcode = MI->getOpcode();
+  bool IsReplaceInstr = false;
+  int NewOpcode = -1;
+
+  auto SetNewOpcode = [&](int NewOpc) {
+    if (!IsReplaceInstr) {
+      NewOpcode = NewOpc;
+      IsReplaceInstr = true;
+    }
+  };
+
+  switch (Opcode) {
+  case PPC::OR:
+    SetNewOpcode(PPC::OR8);
+    [[fallthrough]];
+  case PPC::ISEL:
+    SetNewOpcode(PPC::ISEL8);
+    [[fallthrough]];
+  case PPC::OR8:
+  case PPC::PHI:
+    if (BinOpDepth < MAX_BINOP_DEPTH) {
+      unsigned OperandEnd = 3, OperandStride = 1;
+      if (Opcode == PPC::PHI) {
+        OperandEnd = MI->getNumOperands();
+        OperandStride = 2;
+      }
+
+      for (unsigned I = 1; I != OperandEnd; I += OperandStride) {
+        assert(MI->getOperand(I).isReg() && "Operand must be register");
+        Register SrcReg = MI->getOperand(I).getReg();
+        replaceInstrAfterElimExt32To64(SrcReg, MRI, BinOpDepth + 1, LV);
+      }
+
+      if (!IsReplaceInstr)
+        return;
+    }
+    break;
+  case PPC::COPY: {
+    Register SrcReg = MI->getOperand(1).getReg();
+    const MachineFunction *MF = MI->getMF();
+    if (!MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
+      replaceInstrAfterElimExt32To64(SrcReg, MRI, BinOpDepth, LV);
+      return;
+    }
+    // From here on everything is SVR4ABI
+    if (MI->getParent()->getBasicBlock() == &MF->getFunction().getEntryBlock())
+      return;
+
+    if (SrcReg != PPC::X3) {
+      replaceInstrAfterElimExt32To64(SrcReg, MRI, BinOpDepth, LV);
+      return;
+    }
+  }
+    return;
+  case PPC::ORI:
+    SetNewOpcode(PPC::ORI8);
+    [[fallthrough]];
+  case PPC::XORI:
+    SetNewOpcode(PPC::XORI8);
+    [[fallthrough]];
+  case PPC::ORIS:
+    SetNewOpcode(PPC::ORIS8);
+    [[fallthrough]];
+  case PPC::XORIS:
+    SetNewOpcode(PPC::XORIS8);
+    [[fallthrough]];
+  case PPC::ORI8:
+  case PPC::XORI8:
+  case PPC::ORIS8:
+  case PPC::XORIS8: {
+    Register SrcReg = MI->getOperand(1).getReg();
+    replaceInstrAfterElimExt32To64(SrcReg, MRI, BinOpDepth, LV);
+
+    if (!IsReplaceInstr)
+      return;
+    break;
+  }
+  case PPC::AND:
+    SetNewOpcode(PPC::AND8);
+    [[fallthrough]];
+  case PPC::AND8: {
+    if (BinOpDepth < MAX_BINOP_DEPTH) {
+      Register SrcReg1 = MI->getOperand(1).getReg();
+      replaceInstrAfterElimExt32To64(SrcReg1, MRI, BinOpDepth, LV);
+      Register SrcReg2 = MI->getOperand(2).getReg();
+      replaceInstrAfterElimExt32To64(SrcReg2, MRI, BinOpDepth, LV);
+      if (!IsReplaceInstr)
+        return;
+    }
+    break;
+  }
+  case PPC::RLWINM:
+    SetNewOpcode(PPC::RLWINM8);
+    break;
+  case PPC::RLWINM_rec:
+    SetNewOpcode(PPC::RLWINM8_rec);
+    break;
+  case PPC::RLWNM:
+    SetNewOpcode(PPC ::RLWNM8);
+    break;
+  case PPC::RLWNM_rec:
+    SetNewOpcode(PPC::RLWNM8_rec);
+    break;
+  case PPC::ANDC_rec:
+    SetNewOpcode(PPC::ANDC8_rec);
+    break;
+  case PPC::ANDIS_rec:
+    SetNewOpcode(PPC::ANDIS8_rec);
+    break;
+  default:
+    break;
+  }
+
+  const PPCInstrInfo *TII =
+      MI->getMF()->getSubtarget<PPCSubtarget>().getInstrInfo();
+  if ((definedBySignExtendingOp(Reg, MRI) && !TII->isZExt32To64(Opcode) &&
+       !isOpZeroOfSubwordPreincLoad(Opcode)) ||
+      IsReplaceInstr) {
+
+    const TargetRegisterClass *RC = MRI->getRegClass(Reg);
+
+    if (RC == &PPC::G8RCRegClass || RC == &PPC::G8RC_and_G8RC_NOX0RegClass)
+      return;
+
+    if (!IsReplaceInstr)
+      NewOpcode = PPC::get64BitInstrFromSignedExt32BitInstr(Opcode);
+
+    assert(NewOpcode != -1 &&
+           "Must have a 64-bit opcode to map the 32-bit opcode!");
+
+    const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
+    const MCInstrDesc &MCID = TII->get(NewOpcode);
+
+    Register SrcReg = MI->getOperand(0).getReg();
+    const TargetRegisterClass *NewRC =
+        TRI->getRegClass(MCID.operands()[0].RegClass);
+    const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcReg);
+
+    if (NewRC == SrcRC)
+      return;
+
+    DebugLoc DL = MI->getDebugLoc();
+    auto MBB = MI->getParent();
+
+    // Since the pseudo-opcode of the instruction is promoted from 32-bit to
+    // 64-bit, if the operand of the original instruction belongs to
+    // PPC::GRCRegClass or PPC::GPRC_and_GPRC_NOR0RegClass, we need to promote
+    // the operand to PPC::G8CRegClass or PPC::G8RC_and_G8RC_NOR0RegClass,
+    // respectively.
+    DenseMap<unsigned, Register> PromoteRegs;
+    DenseMap<unsigned, Register> ReCalRegs;
+    for (unsigned i = 1; i < MI->getNumOperands(); i++) {
+      MachineOperand &Operand = MI->getOperand(i);
+      if (Operand.isReg()) {
+        Register OperandReg = Operand.getReg();
+        if (!OperandReg.isVirtual())
+          continue;
+
+        const TargetRegisterClass *RC =
+            TRI->getRegClass(MCID.operands()[i].RegClass);
+        const TargetRegisterClass *OrgRC = MRI->getRegClass(OperandReg);
+        if (RC != MRI->getRegClass(OperandReg) &&
+            (OrgRC == &PPC::GPRCRegClass ||
+             OrgRC == &PPC::GPRC_and_GPRC_NOR0RegClass)) {
+          Register TmpReg = MRI->createVirtualRegister(RC);
+          Register DstTmpReg = MRI->createVirtualRegister(RC);
+          BuildMI(*MBB, MI, DL, TII->get(PPC::IMPLICIT_DEF), TmpReg);
+          BuildMI(*MBB, MI, DL, TII->get(PPC::INSERT_SUBREG), DstTmpReg)
+              .addReg(TmpReg)
+              .addReg(OperandReg)
+              .addImm(PPC::sub_32);
+          PromoteRegs[i] = DstTmpReg;
+          ReCalRegs[i] = DstTmpReg;
+        } else {
+          ReCalRegs[i] = OperandReg;
+        }
+      }
+    }
+
+    Register NewReg = MRI->createVirtualRegister(NewRC);
+
+    BuildMI(*MBB, MI, DL, TII->get(NewOpcode), NewReg);
+    MachineBasicBlock::instr_iterator Iter(MI);
+    --Iter;
+    for (unsigned i = 1; i < MI->getNumOperands(); i++)
+      if (PromoteRegs.find(i) != PromoteRegs.end())
+        MachineInstrBuilder(*Iter->getMF(), Iter)
+            .addReg(PromoteRegs[i], RegState::Kill);
+      else
+        Iter->addOperand(MI->getOperand(i));
+
+    for (auto Iter = ReCalRegs.begin(); Iter != ReCalRegs.end(); Iter++)
+      LV->recomputeForSingleDefVirtReg(Iter->second);
+    MI->eraseFromParent();
+
+    BuildMI(*MBB, ++Iter, DL, TII->get(PPC::COPY), SrcReg)
+        .addReg(NewReg, RegState::Kill, PPC::sub_32);
+    LV->recomputeForSingleDefVirtReg(NewReg);
+    return;
+  }
+  return;
+}
+
 // The isSignOrZeroExtended function is recursive. The parameter BinOpDepth
 // does not count all of the recursions. The parameter BinOpDepth is incremented
 // only when isSignOrZeroExtended calls itself more than once. This is done to

llvm/lib/Target/PowerPC/PPCInstrInfo.h

@@ -17,6 +17,7 @@
 #include "PPC.h"
 #include "PPCRegisterInfo.h"
 #include "llvm/ADT/SmallSet.h"
+#include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 
 #define GET_INSTRINFO_HEADER
@@ -624,6 +625,10 @@ class PPCInstrInfo : public PPCGenInstrInfo {
                       const MachineRegisterInfo *MRI) const {
     return isSignOrZeroExtended(Reg, 0, MRI).second;
   }
+  void replaceInstrAfterElimExt32To64(const Register &Reg,
+                                      MachineRegisterInfo *MRI,
+                                      unsigned BinOpDepth,
+                                      LiveVariables *LV) const;
 
   bool convertToImmediateForm(MachineInstr &MI,
                               SmallSet<Register, 4> &RegsToUpdate,

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

@@ -1051,6 +1051,7 @@ bool PPCMIPeephole::simplifyCode() {
                    TII->isSignExtended(NarrowReg, MRI)) {
           // We can eliminate EXTSW if the input is known to be already
           // sign-extended.
+          TII->replaceInstrAfterElimExt32To64(NarrowReg, MRI, 0, LV);
           LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
           Register TmpReg =
               MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);

llvm/lib/Target/PowerPC/PPCScheduleP7.td

@@ -216,7 +216,7 @@ let SchedModel = P7Model in {
     RLWNM, RLWNM8, RLWNM_rec, RLDIMI, RLDIMI_rec,
     RLDICL_32, RLDICL_32_64, RLDICL_32_rec, RLDICR_32, RLWINM8_rec, RLWNM8_rec,
     SLD, SLD_rec, SLW, SLW8, SLW_rec, SLW8_rec, SRD, SRD_rec, SRW, SRW8, SRW_rec,
-    SRW8_rec, SRADI, SRADI_rec, SRAWI, SRAWI_rec, SRAD, SRAD_rec, SRAW, SRAW_rec,
+    SRW8_rec, SRADI, SRADI_rec, SRAWI, SRAWI_rec, SRAWI8, SRAWI8_rec, SRAD, SRAD_rec, SRAW, SRAW_rec, SRAW8, SRAW8_rec,
     SRADI_32, SUBFE, SUBFE8, SUBFE8O_rec, SUBFEO_rec
   )>;
 

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir

@@ -256,7 +256,7 @@ body:             |
     %3 = IMPLICIT_DEF
     %2 = LI 170
     %4 = RLWNM killed %1, %2, 20, 27
-    ; CHECK: RLWINM killed %1, 10, 20, 27
+    ; CHECK: RLWINM8 killed %6, 10, 20, 27
     ; CHECK-LATE: rlwinm 3, 3, 10, 20, 27
     $x3 = EXTSW_32_64 %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -604,7 +604,7 @@ body:             |
     %2 = LI 48
     %5 = COPY %0.sub_32
     %8 = SRW killed %5, killed %2
-    ; CHECK: LI 0
+    ; CHECK: LI8 0
     ; CHECK-LATE: li 3, 0
     $x3 = EXTSW_32_64 %8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -722,7 +722,7 @@ body:             |
     %3 = COPY %0.sub_32
     %4 = SRAW killed %3, killed %2, implicit-def dead $carry
     ; CHECK: LI 48
-    ; CHECK: SRAW killed %3, killed %2, implicit-def dead $carry
+    ; CHECK: SRAW8 killed %7, killed %9, implicit-def $carry, implicit-def dead $carry 
     ; CHECK-LATE: sraw 3, 3, 4
     %5 = EXTSW_32_64 killed %4
     $x3 = COPY %5
@@ -779,7 +779,7 @@ body:             |
     %2 = LI 80
     %3 = COPY %0.sub_32
     %4 = SRAW_rec killed %3, %2, implicit-def dead $carry, implicit-def $cr0
-    ; CHECK: SRAW_rec killed %3, %2, implicit-def dead $carry, implicit-def $cr0
+    ; CHECK: SRAW8_rec killed %10, killed %12, implicit-def $carry, implicit-def $cr0, implicit-def dead $carry, implicit-def $cr0
     ; CHECK-LATE: sraw. 3, 3, 4
     %5 = COPY killed $cr0
     %6 = ISEL %2, %4, %5.sub_eq