[RISCV] Support rv{32, 64}e in the compiler builtins #88252
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…estore) In RISC-V embedded work differently because there are less registers and different stack alignment. Signed-off-by: xermicus <cyrill@parity.io>
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@xermicus Congratulations on having your first Pull Request (PR) merged into the LLVM Project! Your changes will be combined with recent changes from other authors, then tested Please check whether problems have been caused by your change specifically, as How to do this, and the rest of the post-merge process, is covered in detail here. If your change does cause a problem, it may be reverted, or you can revert it yourself. If you don't get any reports, no action is required from you. Your changes are working as expected, well done! |
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@wangpc-pp thanks for merging! Should this be backported to |
Yeah, I think so! We have supported RVE in 18.x, but it isn't fully supported without this change. |
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/cherry-pick bd32aaa |
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Failed to create pull request for issue88252 https://github.com/llvm/llvm-project/actions/runs/8663009660 |
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/cherry-pick bd32aaa |
Register spills (save/restore) in RISC-V embedded work differently because there are less registers and different stack alignment. [GCC equivalent ](https://github.com/gcc-mirror/gcc/blob/master/libgcc/config/riscv/save-restore.S#L298C16-L336) Follow up from llvm#76777. --------- Signed-off-by: xermicus <cyrill@parity.io> (cherry picked from commit bd32aaa)
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/pull-request #88525 |
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Excellent! I agree |
Register spills (save/restore) in RISC-V embedded work differently because there are less registers and different stack alignment. [GCC equivalent ](https://github.com/gcc-mirror/gcc/blob/master/libgcc/config/riscv/save-restore.S#L298C16-L336) Follow up from llvm#76777. --------- Signed-off-by: xermicus <cyrill@parity.io> (cherry picked from commit bd32aaa)
Register spills (save/restore) in RISC-V embedded work differently because there are less registers and different stack alignment.
GCC equivalent
Follow up from #76777.
CC @koute @wangpc-pp