[hexagon] Add {con,de}structive interference size defn

[androm3da]

This support was originally added in 72c373b ([C++17] Support _GCC[CON|DE]STRUCTIVE_SIZE (#89446), 2024-04-26). We're overriding the values for Hexagon here.

[llvmbot]

@llvm/pr-subscribers-clang

Author: Brian Cain (androm3da)

Changes

This support was originally added in 72c373b ([C++17] Support _GCC[CON|DE]STRUCTIVE_SIZE (#89446), 2024-04-26). We're overriding the values for Hexagon here.

---

Full diff: https://github.com/llvm/llvm-project/pull/94877.diff

1 Files Affected:

• (modified) clang/lib/Basic/Targets/Hexagon.h (+4)

diff --git a/clang/lib/Basic/Targets/Hexagon.h b/clang/lib/Basic/Targets/Hexagon.h
index cdb47dbae7999..f5e7a8878f01b 100644
--- a/clang/lib/Basic/Targets/Hexagon.h
+++ b/clang/lib/Basic/Targets/Hexagon.h
@@ -139,6 +139,10 @@ class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {
   }
 
   bool hasBitIntType() const override { return true; }
+
+  std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
+    return std::make_pair(32, 32);
+  }
 };
 } // namespace targets
 } // namespace clang

[AaronBallman]

LGTM as far as the code goes, but please add some test coverage for the changes.

[androm3da]

LGTM as far as the code goes, but please add some test coverage for the changes.

Not sure why I omitted it -- thanks. Fixed.

[androm3da]

I was mistaken: it appears that the cache line size is not the same among all CPUs. I'll revise this PR.

Since I'm away from the office for a couple of weeks, I've switched this PR to a draft. I'll revisit it when I return and promote it when updated.

[AaronBallman]

LGTM, thank you!