BRAM Utilization

[AhmadHouraniah]

Hello,

I am generating an FPGA with BRAMs. However, I am having issues with the simulation. If the BRAMs outputs go through some additional logic (even just flip flops), the output from the FPGA DUT is X's. It seems like there's a multiple-driver issue where something else on the FPGA fabric is also driving the BRAM's outputs.
If the BRAM's outputs are directly used as the benchmark's outputs, the simulation runs fine.

I'm using the preconfig_testbench_explicit_mapping task. But I've added a custom benchmark to utlize the BRAM, I'm also directly instantiating the BRAM so that Yosys will always map it to the BRAM.
Benchmark: counter_bram.zip

"flag" is just connected to the flopped LSB of the BRAM's output, the addresses I'm reading from will always produce 1.

Does anyone have a suggestion for what could be causing this behavior?

[AhmadHouraniah]

The issue seems to be related to preconfigured TBs only.
Testing the same example with a different task that uses a full TB fixes the issue. It looks like I'm running into a bug but I haven't identified the exact cause.