Now preconfigured Verilog wrapper can handle config_enable signals correctly

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue:
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

Currently, OpenFPGA has the following limitations:

• config_enable ports of circuit models are not handled correctly in preconfigured Verilog wrapper
  • config_enable signals are designed to be pulled up/down once FPGA bitstream loading is done. In OpenFPGA architecture description, their default values are given as the initial values to be set when bitstream loading is ongoing.
  • However, in preconfigured wrappers. The configuration is already done. So the config_enable signals should be set to the default values. Instead, they should be set to the opposite to the default values

What does this pull request change?

This PR improves in the following aspects:

• Now preconfigured Verilog wrapper can handle config_enable signals correctly
• Update documentation on the config_enable signals, regarding their values in testbenches
• Add dedicated test cases to validate this feature

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.