Support Negative Edge Flip-flop

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue:
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

Currently, OpenFPGA has the following limitations:

• No examples about how to use negative edge triggered flip-flops

What does this pull request change?

This PR improves in the following aspects:

• Added a new circuit design of multi-mode flip-flop which supports negative-edge and positive edge
• Added a regression test for compiling verilog files in cell library
• Added an architecture which supported both positive edge and negative edge triggered flip-flops
• Added a counter design which is triggered by negative edge
• Added a test case to validate the newly added benchmark and architecture

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.

[tangxifan]

Waveform of the test case: