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[dv] Add spurious responses to memory agent #176

[dv] Add spurious responses to memory agent

[dv] Add spurious responses to memory agent #176

Triggered via pull request July 2, 2024 15:15
Status Failure
Total duration 1m 0s
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pr_lint.yml

on: pull_request
verible-lint
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verible-lint
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1 error and 4 warnings
verible-lint
Process completed with exit code 1.
verible-lint: dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L165
[verible-verilog-lint] reported by reviewdog 🐶 Line length exceeds max: 100; is: 123 [Style: line-length] [line-length] Raw Output: message:"Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:165 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
verible-lint: dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L166
[verible-verilog-lint] reported by reviewdog 🐶 Line length exceeds max: 100; is: 112 [Style: line-length] [line-length] Raw Output: message:"Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:166 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
verible-lint: dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L167
[verible-verilog-lint] reported by reviewdog 🐶 Line length exceeds max: 100; is: 106 [Style: line-length] [line-length] Raw Output: message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:167 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
verible-lint: dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L170
[verible-verilog-lint] reported by reviewdog 🐶 Line length exceeds max: 100; is: 156 [Style: line-length] [line-length] Raw Output: message:"Line length exceeds max: 100; is: 156 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:170 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}