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[pmp] Use top-level straps for PMP reset values
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By using top-level straps for the PMP reset configuration its
easier to implement different reset configurations if there are
multiple Ibex cores in the system.

Signed-off-by: Robert Schilling <rschilling@rivosinc.com>
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@Razer6
Razer6 committed Mar 1, 2024
1 parent d8cbab0 commit 392f556
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Showing 8 changed files with 173 additions and 160 deletions.
4 changes: 2 additions & 2 deletions doc/03_reference/pmp.rst
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Expand Up @@ -50,5 +50,5 @@ Custom Reset Values

By default all PMP CSRs (include ``mseccfg``) are reset to 0.
Some applications may want other reset values.
Default reset values are defined in :file:`ibex_pmp_reset_default.svh`.
An implementation can either modify this file or define ``IBEX_CUSTOM_PMP_RESET_VALUES`` and place a copy of :file:`ibex_pmp_result_default.svh` in a new file, :file:`ibex_pmp_reset.svh`, changing the values as required and adding the new file to the include path of whatever build flow is being used.
Default reset values are defined in :file:`ibex_pkg.svh`.
An implementation can either modify this file or pass custom reset values as a module parameter.
1 change: 0 additions & 1 deletion ibex_core.core
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Expand Up @@ -35,7 +35,6 @@ filesets:
- rtl/ibex_wb_stage.sv
- rtl/ibex_dummy_instr.sv
- rtl/ibex_core.sv
- rtl/ibex_pmp_reset_default.svh: {is_include_file: true}
file_type: systemVerilogSource

files_lint_verilator:
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64 changes: 35 additions & 29 deletions rtl/ibex_core.sv
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Expand Up @@ -14,35 +14,38 @@
* Top level module of the ibex RISC-V core
*/
module ibex_core import ibex_pkg::*; #(
parameter bit PMPEnable = 1'b0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
parameter int unsigned MHPMCounterNum = 0,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit RV32E = 1'b0,
parameter rv32m_e RV32M = RV32MFast,
parameter rv32b_e RV32B = RV32BNone,
parameter bit BranchTargetALU = 1'b0,
parameter bit WritebackStage = 1'b0,
parameter bit ICache = 1'b0,
parameter bit ICacheECC = 1'b0,
parameter int unsigned BusSizeECC = BUS_SIZE,
parameter int unsigned TagSizeECC = IC_TAG_SIZE,
parameter int unsigned LineSizeECC = IC_LINE_SIZE,
parameter bit BranchPredictor = 1'b0,
parameter bit DbgTriggerEn = 1'b0,
parameter int unsigned DbgHwBreakNum = 1,
parameter bit ResetAll = 1'b0,
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
parameter bit SecureIbex = 1'b0,
parameter bit DummyInstructions = 1'b0,
parameter bit RegFileECC = 1'b0,
parameter int unsigned RegFileDataWidth = 32,
parameter bit MemECC = 1'b0,
parameter int unsigned MemDataWidth = MemECC ? 32 + 7 : 32,
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808
parameter bit PMPEnable = 1'b0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
parameter ibex_pkg::pmp_cfg_t PMPRstCfg[16] = ibex_pkg::pmp_cfg_rst,
parameter logic [33:0] PMPRstAddr[16] = ibex_pkg::pmp_addr_rst,
parameter ibex_pkg::pmp_mseccfg_t PMPRstMsecCfg = ibex_pkg::pmp_mseccfg_rst,
parameter int unsigned MHPMCounterNum = 0,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit RV32E = 1'b0,
parameter rv32m_e RV32M = RV32MFast,
parameter rv32b_e RV32B = RV32BNone,
parameter bit BranchTargetALU = 1'b0,
parameter bit WritebackStage = 1'b0,
parameter bit ICache = 1'b0,
parameter bit ICacheECC = 1'b0,
parameter int unsigned BusSizeECC = BUS_SIZE,
parameter int unsigned TagSizeECC = IC_TAG_SIZE,
parameter int unsigned LineSizeECC = IC_LINE_SIZE,
parameter bit BranchPredictor = 1'b0,
parameter bit DbgTriggerEn = 1'b0,
parameter int unsigned DbgHwBreakNum = 1,
parameter bit ResetAll = 1'b0,
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
parameter bit SecureIbex = 1'b0,
parameter bit DummyInstructions= 1'b0,
parameter bit RegFileECC = 1'b0,
parameter int unsigned RegFileDataWidth = 32,
parameter bit MemECC = 1'b0,
parameter int unsigned MemDataWidth = MemECC ? 32 + 7 : 32,
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808
) (
// Clock and Reset
input logic clk_i,
Expand Down Expand Up @@ -1019,6 +1022,9 @@ module ibex_core import ibex_pkg::*; #(
.PMPEnable (PMPEnable),
.PMPGranularity (PMPGranularity),
.PMPNumRegions (PMPNumRegions),
.PMPRstCfg (PMPRstCfg),
.PMPRstAddr (PMPRstAddr),
.PMPRstMsecCfg (PMPRstMsecCfg),
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B)
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46 changes: 21 additions & 25 deletions rtl/ibex_cs_registers.sv
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Expand Up @@ -10,20 +10,23 @@
`include "prim_assert.sv"

module ibex_cs_registers #(
parameter bit DbgTriggerEn = 0,
parameter int unsigned DbgHwBreakNum = 1,
parameter bit DataIndTiming = 1'b0,
parameter bit DummyInstructions = 1'b0,
parameter bit ShadowCSR = 1'b0,
parameter bit ICache = 1'b0,
parameter int unsigned MHPMCounterNum = 10,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit PMPEnable = 0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
parameter bit RV32E = 0,
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone
parameter bit DbgTriggerEn = 0,
parameter int unsigned DbgHwBreakNum = 1,
parameter bit DataIndTiming = 1'b0,
parameter bit DummyInstructions = 1'b0,
parameter bit ShadowCSR = 1'b0,
parameter bit ICache = 1'b0,
parameter int unsigned MHPMCounterNum = 10,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit PMPEnable = 0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
parameter ibex_pkg::pmp_cfg_t PMPRstCfg[16] = ibex_pkg::pmp_cfg_rst,
parameter logic [33:0] PMPRstAddr[16] = ibex_pkg::pmp_addr_rst,
parameter ibex_pkg::pmp_mseccfg_t PMPRstMsecCfg = ibex_pkg::pmp_mseccfg_rst,
parameter bit RV32E = 0,
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone
) (
// Clock and Reset
input logic clk_i,
Expand Down Expand Up @@ -1073,13 +1076,6 @@ module ibex_cs_registers #(
// -----------------

if (PMPEnable) begin : g_pmp_registers
// PMP reset values
`ifdef IBEX_CUSTOM_PMP_RESET_VALUES
`include "ibex_pmp_reset.svh"
`else
`include "ibex_pmp_reset_default.svh"
`endif

pmp_mseccfg_t pmp_mseccfg_q, pmp_mseccfg_d;
logic pmp_mseccfg_we;
logic pmp_mseccfg_err;
Expand Down Expand Up @@ -1168,7 +1164,7 @@ module ibex_cs_registers #(
ibex_csr #(
.Width ($bits(pmp_cfg_t)),
.ShadowCopy(ShadowCSR),
.ResetValue(pmp_cfg_rst[i])
.ResetValue(PMPRstCfg[i])
) u_pmp_cfg_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
Expand Down Expand Up @@ -1203,7 +1199,7 @@ module ibex_cs_registers #(
ibex_csr #(
.Width (PMPAddrWidth),
.ShadowCopy(ShadowCSR),
.ResetValue(pmp_addr_rst[i][33-:PMPAddrWidth])
.ResetValue(PMPRstAddr[i][33-:PMPAddrWidth])
) u_pmp_addr_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
Expand All @@ -1213,7 +1209,7 @@ module ibex_cs_registers #(
.rd_error_o(pmp_addr_err[i])
);

`ASSERT_INIT(PMPAddrRstLowBitsZero_A, pmp_addr_rst[i][33-PMPAddrWidth:0] == '0)
`ASSERT_INIT(PMPAddrRstLowBitsZero_A, PMPRstAddr[i][33-PMPAddrWidth:0] == '0)

assign csr_pmp_cfg_o[i] = pmp_cfg[i];
assign csr_pmp_addr_o[i] = {pmp_addr_rdata[i], 2'b00};
Expand All @@ -1236,7 +1232,7 @@ module ibex_cs_registers #(
ibex_csr #(
.Width ($bits(pmp_mseccfg_t)),
.ShadowCopy(ShadowCSR),
.ResetValue(pmp_mseccfg_rst)
.ResetValue(PMPRstMsecCfg)
) u_pmp_mseccfg (
.clk_i (clk_i),
.rst_ni (rst_ni),
Expand Down
62 changes: 34 additions & 28 deletions rtl/ibex_lockstep.sv
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Expand Up @@ -9,36 +9,39 @@

// SEC_CM: LOGIC.SHADOW
module ibex_lockstep import ibex_pkg::*; #(
parameter int unsigned LockstepOffset = 2,
parameter bit PMPEnable = 1'b0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
parameter int unsigned MHPMCounterNum = 0,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit RV32E = 1'b0,
parameter rv32m_e RV32M = RV32MFast,
parameter rv32b_e RV32B = RV32BNone,
parameter bit BranchTargetALU = 1'b0,
parameter bit WritebackStage = 1'b0,
parameter bit ICache = 1'b0,
parameter bit ICacheECC = 1'b0,
parameter int unsigned BusSizeECC = BUS_SIZE,
parameter int unsigned TagSizeECC = IC_TAG_SIZE,
parameter int unsigned LineSizeECC = IC_LINE_SIZE,
parameter bit BranchPredictor = 1'b0,
parameter bit DbgTriggerEn = 1'b0,
parameter int unsigned DbgHwBreakNum = 1,
parameter bit ResetAll = 1'b0,
parameter int unsigned LockstepOffset = 2,
parameter bit PMPEnable = 1'b0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
parameter ibex_pkg::pmp_cfg_t PMPRstCfg[16] = ibex_pkg::pmp_cfg_rst,
parameter logic [33:0] PMPRstAddr[16] = ibex_pkg::pmp_addr_rst,
parameter ibex_pkg::pmp_mseccfg_t PMPRstMsecCfg = ibex_pkg::pmp_mseccfg_rst,
parameter int unsigned MHPMCounterNum = 0,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit RV32E = 1'b0,
parameter rv32m_e RV32M = RV32MFast,
parameter rv32b_e RV32B = RV32BNone,
parameter bit BranchTargetALU = 1'b0,
parameter bit WritebackStage = 1'b0,
parameter bit ICache = 1'b0,
parameter bit ICacheECC = 1'b0,
parameter int unsigned BusSizeECC = BUS_SIZE,
parameter int unsigned TagSizeECC = IC_TAG_SIZE,
parameter int unsigned LineSizeECC = IC_LINE_SIZE,
parameter bit BranchPredictor = 1'b0,
parameter bit DbgTriggerEn = 1'b0,
parameter int unsigned DbgHwBreakNum = 1,
parameter bit ResetAll = 1'b0,
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
parameter bit SecureIbex = 1'b0,
parameter bit DummyInstructions = 1'b0,
parameter bit RegFileECC = 1'b0,
parameter int unsigned RegFileDataWidth = 32,
parameter bit MemECC = 1'b0,
parameter int unsigned MemDataWidth = MemECC ? 32 + 7 : 32,
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808
parameter bit SecureIbex = 1'b0,
parameter bit DummyInstructions = 1'b0,
parameter bit RegFileECC = 1'b0,
parameter int unsigned RegFileDataWidth = 32,
parameter bit MemECC = 1'b0,
parameter int unsigned MemDataWidth = MemECC ? 32 + 7 : 32,
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -347,6 +350,9 @@ module ibex_lockstep import ibex_pkg::*; #(
.PMPEnable ( PMPEnable ),
.PMPGranularity ( PMPGranularity ),
.PMPNumRegions ( PMPNumRegions ),
.PMPRstCfg ( PMPRstCfg ),
.PMPRstAddr ( PMPRstAddr ),
.PMPRstMsecCfg ( PMPRstMsecCfg ),
.MHPMCounterNum ( MHPMCounterNum ),
.MHPMCounterWidth ( MHPMCounterWidth ),
.RV32E ( RV32E ),
Expand Down
50 changes: 50 additions & 0 deletions rtl/ibex_pkg.sv
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Expand Up @@ -664,4 +664,54 @@ package ibex_pkg;
// and core_busy signals within `ibex_core` may need adjusting.
parameter ibex_mubi_t IbexMuBiOn = 4'b0101;
parameter ibex_mubi_t IbexMuBiOff = 4'b1010;

// Default reset values for PMP CSRs. Where the number of regions
// (PMPNumRegions) is less than 16 the reset values for the higher numbered
// regions are ignored.
//
// See the Ibex Reference Guide (Custom Reset Values under Physical Memory
// Protection) for more information.

parameter pmp_cfg_t pmp_cfg_rst[16] = '{

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Non-type parameter names must be styled with CamelCase or ALL_CAPS [Style: constants] [parameter-name-style]

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message:"Non-type parameter names must be styled with CamelCase or ALL_CAPS [Style: constants] [parameter-name-style]"  location:{path:"./rtl/ibex_pkg.sv"  range:{start:{line:675  column:23}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 0
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 1
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 2
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 3
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 4
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 5
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 6
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 7
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 8
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 9
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 10
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 11
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 12
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 13
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 14
'{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0} // region 15
};

// Addresses are given in byte granularity for readibility. A minimum of two
// bits will be stripped off the bottom (PMPGranularity == 0) with more stripped
// off at coarser granularities.
parameter logic [33:0] pmp_addr_rst[16] = '{

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Non-type parameter names must be styled with CamelCase or ALL_CAPS [Style: constants] [parameter-name-style]

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message:"Non-type parameter names must be styled with CamelCase or ALL_CAPS [Style: constants] [parameter-name-style]"  location:{path:"./rtl/ibex_pkg.sv"  range:{start:{line:697  column:26}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
34'h0, // region 0
34'h0, // region 1
34'h0, // region 2
34'h0, // region 3
34'h0, // region 4
34'h0, // region 5
34'h0, // region 6
34'h0, // region 7
34'h0, // region 8
34'h0, // region 9
34'h0, // region 10
34'h0, // region 11
34'h0, // region 12
34'h0, // region 13
34'h0, // region 14
34'h0 // region 15
};

parameter pmp_mseccfg_t pmp_mseccfg_rst = '{rlb : 1'b0, mmwp: 1'b0, mml: 1'b0};

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Non-type parameter names must be styled with CamelCase or ALL_CAPS [Style: constants] [parameter-name-style]

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message:"Non-type parameter names must be styled with CamelCase or ALL_CAPS [Style: constants] [parameter-name-style]"  location:{path:"./rtl/ibex_pkg.sv"  range:{start:{line:716  column:27}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
endpackage
53 changes: 0 additions & 53 deletions rtl/ibex_pmp_reset_default.svh
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