Update lowrisc_ip to lowRISC/opentitan@e619fc60

This updates the vendored code from OpenTitan and fixes up patches as we go. The biggest change is that the support files that were in dv/data have moved to dv/tools/dvsim (with a couple of other internal renames). The icache test code also needs the corresponding path change and to rename its regression from "sanity" to "smoke" (the new name for the default regression). Update code from upstream repository https://github.com/lowRISC/opentitan to revision e619fc60c6b9c755043eba65a41dc47815612834 * [dv] Remove duplicated keys from common_sim_cfg.hjson (Rupert Swarbrick) * [dv] two small fix in dv (Cindy Chen) * [dv] Comment out example build modes from common_sim_cfg.hjson (Rupert Swarbrick) * [dv/keymgr] Cleanup some warnings in xcelium (Weicai Yang) * [lc_ctrl] Reuse an instance of the RISC-V dmi_jtag as the LC TAP (Michael Schaffner) * [otp_ctrl] Update LC types within OTP (Michael Schaffner) * [lc_ctrl] Add first cut implementation (Michael Schaffner) * [flash_ctrl] update prim flash interface (Timothy Chen) * [flash_ctrl] Add support for isolated flash partition (Timothy Chen) * [dv/common] update naming from sanity to smoke (Cindy Chen) * [prim] update naming from sanity to smoke (Cindy Chen) * [dv/base] add get_reg_by_name support in dv_base_reg_block (Cindy Chen) * [cov methodology] Functional coverage prototype (Srikrishna Iyer) * [dv] Fix tpyo (Weicai Yang) * [dv common] Wave dumping improvements / fix (Srikrishna Iyer) * [dv] Fix for `--run-only` switch (Srikrishna Iyer) * [prim_present] Add support for iterative full-round PRESENT (Michael Schaffner) * [dv] Fix VCS compile error (Weicai Yang) * [sparse-fsm-encode] Switch to Safe Rust Encoding (Sam Elliott) * [sparse-fsm-encode] Disallow Complementary Encodings (Sam Elliott) * [prim/util] Fix parameter type when using prefixes (Pirmin Vogel) * [keymgr/prim_lfsr] Correct minor errors in core files (Michael Schaffner) * [design checklist] avoid using word sanity (Cindy Chen) * [prim_lc_sync] Add two stage sync for life cycle control signals (Michael Schaffner) * [flash] update flash program to support ack / done / last (Timothy Chen) * [prim] update prim flash to have ack / done support (Timothy Chen) * Fix typo in testplan template (Rupert Swarbrick) * [dv] Fix license header for some cfg files (Weicai Yang) * [dv] Only check scoreboard from pre_abort if we were in run phase (Rupert Swarbrick) * [doc] Add lint requirements to V1 checklist (Cindy Chen) * [dv common] Minor enhancements to dv_reg_block (Srikrishna Iyer) * [dv] Fix library paths for dsim (Srikrishna Iyer) * [keymgr/dv] Update testbench (Weicai Yang) * [dv/common] Add DV_ALERT_IF_CONNECT macro (Weicai Yang) * [dv, common] Promote VCS warning to error (Srikrishna Iyer) * [prim] update clock_mux prim to avoid using BUFG (Timothy Chen) * [clkmgr] Add divider bypass during test mode (Timothy Chen) * [opt_ctrl] Change state_q assignment to ease debugging (Michael Schaffner) * [doc] Update D2 checklist and propagate updates to IPs (Michael Schaffner) * [dv/dvsim] Fix -c option compile error (Cindy Chen) * [dv] Tidy up use of get_normalized_addr (Rupert Swarbrick) * [fpv] Fix fusesoc dependecy issue (Cindy Chen) * [lint] Fix lint warning (Cindy Chen) * [dv/lint] Add new DV TB to lint batch script (Cindy Chen) * [fpv] Add lint checking to FPV tb (Cindy Chen) * [dvsim] Remove process_exports() from the code (Srikrishna Iyer) * [dvsim] Fix HJson bugs (Srikrishna Iyer) * [fpv] alert_rx/tx updates (Cindy Chen) * [prim] slicer lint fix (Eunchan Kim) * [prim] Packer to remove unused parameter. (Eunchan Kim) * [prim_lfsr] Update prim_lfsr and testbench to use correct perm width (Michael Schaffner) * [prim_lfsr] Add script to generate seed and perm constants (Michael Schaffner) * [dv/common] Upgrade some VCS warnings to errors (Weicai Yang) * [dvsim] Document and slightly improve subst_wildcards in utils.py (Rupert Swarbrick) * [csrng/dv] Initial dv environment (Steve Nelson) * [sparse-fsm-encode] Update template to prevent JG compile error (Michael Schaffner) * Gracefully shut down Verilator when software test fails (Philipp Wagner) * [otp] fix FPV compile error (Cindy Chen) * [dvsim] Kill subprocesses more gracefully (Rupert Swarbrick) * [prim] Fix Verilator lint warnings (Pirmin Vogel) * [memutil] Allocate the right number of bytes in StagedMem::GetFlat() (Rupert Swarbrick) * [memutil] Load ELF files via a staging area (Rupert Swarbrick) * [memutil] Add iterator and merging insertion interfaces to RangedMap (Rupert Swarbrick) * [memutil] Factor out "ranged map" implementation from dpi_memutil (Rupert Swarbrick) * [alert_handler] update alert hander ports (Timothy Chen) * [otp_ctrl] Update OTP output data mapping (Michael Schaffner) * [otp_ctrl] Split partition metadata into separate package (Michael Schaffner) * [prim_otp] Add TL-UL regfile for testing (sim only) (Michael Schaffner) * [memutil] Split out the non-verilator part of verilator_memutil (Rupert Swarbrick) * [dv/common] Update DV_CHECK_* macros (Weicai Yang) * [dv/common] Fix testplan path (Weicai Yang) * [prim_assert] Fixed non-UVM part of `ASSERT_ERROR (Srikrishna Iyer) * [otp_ctrl] Simplify and consolidate OTP error codes (Michael Schaffner) * [kmac] Fix critical syntax errors. (Eunchan Kim) * [dv/common] Move testplan from tools directory to data (Weicai Yang) * [dvsim] Rename verbosity wildcards to something more informative (Rupert Swarbrick) * [dv/lfsr] Update prim_lfsr_sim_cfg.hjson and add coverage (Udi Jonnalagadda) * [dv common] Added string check macros (Srikrishna Iyer) * [rtl] Use platform-agnostic log macros prim_assert (Srikrishna Iyer) * [dv] Minor fixups to dv_Utils_pkg (Srikrishna Iyer) * [dv] Fix platform-agnostic log macros (Srikrishna Iyer) * [checklist] Upgrade wording for D1 milestone (Scott Johnson) * [entropy_src/rtl] fix for dv sanity test (Mark Branstad) * [lint] Add option to bail out on first invalid Tcl cmd (Michael Schaffner) * [sram_ctrl] Add first cut implementation (Michael Schaffner) * [prim] Fix AscentLint waiver that made the tool crash (Michael Schaffner) * [checklists] Clean up and align HW and SW checklists (Michael Schaffner) * [prim] Update signal name in lint waiver rule (Pirmin Vogel) * [flash_ctrl] Switch to new keyschedule in PRINCE (Michael Schaffner) * [lint] fix the waiver format (Eunchan Kim) * [dv] Waive lint warnings in dv_macros.svh (Srikrishna Iyer) * [dv common] Add platform-agnostic log macros (Srikrishna Iyer) * [util] Add Rust Enum Support to sparse-fsm-encode.py (Sam Elliott) * [util] Add C Enum Support to sparse-fsm-encode.py (Sam Elliott) * [sparse-fsm-encode] Expand error and help messages (Michael Schaffner) * [dv/common] TLUL agent function coverage (Weicai Yang) * [dv/shadow_reg] support alert handshake checking (Cindy Chen) * [prim_present/otp_ctrl] Add round index state IOs to primitive (Michael Schaffner) * [dv] Fix 2 regression failures (Weicai Yang) * [prim_multibit_sync] Add multibit synchronizer with consistency check (Michael Schaffner) * [prim] Fix Lint warning for prim_slicer (Eunchan Kim) * [prim_generic_otp] Add TL-UL test interface stub for DV (Michael Schaffner) * [doc] Improve documentation for common_ifs (Rupert Swarbrick) * [doc] Improve pins_if block diagram (Rupert Swarbrick) * [prim_prince/present] Remove TODOs (Michael Schaffner) * [dv/common] Change TL item content when it's not accepted (Weicai Yang) * [dv/uvmgen] update has_alerts (Cindy Chen) * [dv/common] Add run opt plusarg to enable file path in the log (Weicai Yang) * [prim] Add clock buffer primitive for Xilinx FPGAs (Pirmin Vogel) * [otp_ctrl] Provision power sequencing signals (Michael Schaffner) * [dv/common] Clean up old makefile flow (Weicai Yang) * [entropy_src/rtl] review round2 changes (Mark Branstad) * [otp_ctrl] Update all FSMs to use prim_flop for the state (Michael Schaffner) * [prim_xilinx_flop] Add a Xilinx version with keep attribute (Michael Schaffner) * [prim/util] Update sparse-fsm-encode and include FSM template (Michael Schaffner) * [DV macros] minor enhancement to `DV_SPINWAIT (Srikrishna Iyer) * [DV common] Add DV_ASSERT_CTRL macro (Srikrishna Iyer) * [DV common] Enhance `DV_CHECK_MEMBER_RANDOMIZE_*` (Srikrishna Iyer) * [otbn] Use relative scope names for OTBN scopes (Rupert Swarbrick) * [verilator simutil] Add support for relative scope names to SVScoped (Rupert Swarbrick) * [fpv/prim_packer] remove assumption (Cindy Chen) * [fpv/csr_assert] support all modules for CSR assert (Cindy Chen) * [memutil] Teach verilator_memutil to load multi-segment ELF files (Rupert Swarbrick) * [memutil] Simplify how we read ELF files in verilator_memutil.cc (Rupert Swarbrick) * [memutil] Add a "verbose" flag to detail memory loads (Rupert Swarbrick) * [memutil] Parse all arguments before loading anything (Rupert Swarbrick) * [memutil] Use override keyword, not virtual for overridden method (Rupert Swarbrick) * [memutil] Use exceptions to simplify error handling (Rupert Swarbrick) * [memutil] Store the width of memory areas in bytes, not bits (Rupert Swarbrick) * [memutil] Allow memory locations to have associated LMAs (Rupert Swarbrick) * [memutil] Improve type of ElfFileToBinary in verilator_memutil.cc (Rupert Swarbrick) * [verilator simutil] Move SVScoped class into dv/verilator/cpp (Rupert Swarbrick) * [memutil] Move static functions out of VerilatorMemUtil class (Rupert Swarbrick) * [memutil] Run clang-format on verilator_memutil.* (Rupert Swarbrick) * [dv:entropy_src] Initial rng_agent and integrated into entropy_src env (Steve Nelson) * [prim_ram_adv/fpv] fix assertion (Cindy Chen) * [prim_ram_1p_scr] Simplify nonce input and align to multiples of 64b (Michael Schaffner) * [fpv/csr_assert] add csr support for regwen (Cindy Chen) * [prim*] Various lint fixes in the prims (Michael Schaffner) * [prim] remove FPV related assertions (Eunchan Kim) * [prim_lfsr] Add option to supply custom output permutation (Michael Schaffner) * [dv/common] calculate addr map size in RAL (Weicai Yang) * [flash_ctrl] Add ECC to program / erase datapaths (Timothy Chen) * [otp_ctrl] First cut implementation of the OTP controller (Michael Schaffner) * Fix invalid read in verilator_memutil (Rupert Swarbrick) * [doc] Don't strip markdown headings from HW checklist (Philipp Wagner) * [site] Set lint title (Tobias Wölfel) * [dv/prim] add basic PRINCE testbench (Udi Jonnalagadda) * [flash_ctrl] Support the notion of a 'program-repair'. (Timothy Chen) * [prim/tlul] Various small lint fixes (Michael Schaffner) * [dv/uvmdvgen] update dvsim and remove Makefile (Cindy Chen) * [util] Add script for generating sparse FSM encodings (Michael Schaffner) * [prim] Add option to register output for interrupts (Timothy Chen) * [prim_otp] First cut implementation of FPGA emulation (Michael Schaffner) * [prim_ram_1p_adv] Add 16bit ECC mode (Michael Schaffner) * [chip dv] Fix for failing GPIO test (Srikrishna Iyer) * [RTl] Generic pad wrapper default behavior fix (Srikrishna Iyer) * [slicer] Select partial from bitstream (Eunchan Kim) * [util] Don't hack __repr__ in FlowCfg (Rupert Swarbrick) * [util] Fix lint in dvsim.py (Rupert Swarbrick) * [fpv/prim_packer] Add a FPV TB (Cindy Chen) * [Keccak] Keccak_f implementation (Eunchan Kim) * [dv/csr] add common task for csr_or_field_rd_check (Cindy Chen) * [keccak] Add valid signal to random value (Eunchan Kim) * [prim] Add primitive clock divider (Timothy Chen) * [dv/shadow_reg] update sequence for storage error (Cindy Chen) * [dv/lib] clear csr_outstanding_access after reset (Cindy Chen) * [sw] Ensure Headers are Correctly Ordered (Sam Elliott) * [dv] Fix csr_rd check during reset (Weicai Yang) * Adding the first update to coverage methodology (Rasmus Madsen) * [dv] TL agent supports no clock reset (Weicai Yang) * [tlul/dv] Update test plan for tl errors (Weicai Yang) * [fpv/alert] update namings for FPV tb (Cindy Chen) * [keccak] Masked/Unmasked Keccak single round (Eunchan Kim) * [lint/prim*] Waive STAR_PORT_CONN_USE errors in generated prims (Michael Schaffner) * [prim_usb_diff_rx] Carry over wrapper for USB diff receiver (Michael Schaffner) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
lowRISC · Nov 28, 2020 · 4852e30 · 4852e30
1 parent 31a18ad
commit 4852e30
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diff --git a/dv/uvm/icache/dv/Makefile b/dv/uvm/icache/dv/Makefile
@@ -25,7 +25,7 @@ default-seed := 123
 SEED=$(if $(filter 1,$(RESEED)),$(default-seed),)
 
 # Specify which tests to run. Defaults to the empty string, which
-# means dvsim will run its default (the "sanity" suite).
+# means dvsim will run its default (the "smoke" suite of tests).
 TESTS=
 
 ibex-top       := ../../../..

diff --git a/dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson b/dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson
@@ -23,7 +23,7 @@
   // Import additional common sim cfg files.
   import_cfgs: [
       // Project wide common sim cfg file
-      "{proj_root}/vendor/lowrisc_ip/dv/data/common_sim_cfg.hjson"
+      "{proj_root}/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson"
   ]
 
   build_modes: [
@@ -111,7 +111,7 @@
   // List of regressions.
   regressions: [
     {
-      name: sanity
+      name: smoke
       tests: ["ibex_icache_sanity",
               "ibex_icache_passthru",
               "ibex_icache_caching",

diff --git a/vendor/lowrisc_ip.lock.hjson b/vendor/lowrisc_ip.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/lowRISC/opentitan
-    rev: 92e9242424c72c59008e267dd3779e2af5ec8e83
+    rev: e619fc60c6b9c755043eba65a41dc47815612834
   }
 }
diff --git a/vendor/lowrisc_ip.vendor.hjson b/vendor/lowrisc_ip.vendor.hjson
@@ -11,20 +11,10 @@
     }
 
     mapping: [
-        // We have to apply a patch to the vendored files from hw/dv/data,
-        // because they contain an OpenTitan specific path.
-        {
-            from:      "hw/dv/data",
-            to:        "dv/data",
-            patch_dir: "dv_data"
-        },
-
         {from: "hw/dv/sv/common_ifs",  to: "dv/sv/common_ifs"},
         {from: "hw/dv/sv/csr_utils",   to: "dv/sv/csr_utils"},
         {from: "hw/dv/sv/dv_base_reg", to: "dv/sv/dv_base_reg"},
         {from: "hw/dv/sv/mem_model",   to: "dv/sv/mem_model"},
-        {from: "hw/dv/tools",          to: "dv/tools"},
-        {from: "hw/dv/verilator",      to: "dv/verilator"},
 
         // We apply a patch to fix the bus_params_pkg core file name when
         // vendoring in dv_lib and dv_utils. This allows us to have an
@@ -39,6 +29,15 @@
             to:        "dv/sv/dv_utils",
             patch_dir: "dv_utils",
         },
+        // We have to apply a patch to the vendored files from hw/dv/tools
+        // because they contain OpenTitan specific paths.
+        {
+            from:      "hw/dv/tools",
+            to:        "dv/tools",
+            patch_dir: "dv_tools"
+        },
+
+        {from: "hw/dv/verilator",      to: "dv/verilator"},
 
         {from: "hw/ip/prim",           to: "ip/prim"},
         {from: "hw/ip/prim_generic",   to: "ip/prim_generic"},

diff --git a/vendor/lowrisc_ip/dv/sv/common_ifs/index.md b/vendor/lowrisc_ip/dv/sv/common_ifs/index.md
@@ -8,74 +8,79 @@ connecting dut signals. They are described in detail below.
 
 ### `clk_if`
 This is a passive clock interface that is used to wait for clock events in
-testbenches.
-This interface has two clocking blocks: `cb` and `cbn` for synchronizing to
-positive and negative clock edges. This interface consists of following tasks:
+testbenches. This interface has two clocking blocks, `cb` and `cbn`, for
+synchronizing to positive and negative clock edges, respectively. The interface
+also has the following tasks:
 * `wait_clks`: waits for specified number of positive clock edges
 * `wait_n_clks`: waits for specified number of negative clock edges
 
 ### `clk_rst_if`
-This interface provides the ability to drive / sample clock and reset signal.
-It provides various methods related to clock and reset generation. These
-methods can be categorized into `setup methods` and `drive / sample` methods.
-Following are `setup methods` of `pins_if`:
-* `set_freq_mhz`: set the clk frequency in mhz and calclate period in ns
-* `set_duty_cycle`: set the duty cycle (1-99)
-* `set_active`: enables `clk` and `rst_n` generation
-   typically, called at t=0 (from tb top)
-* `set_period_ns`: set the clk period in ns and calculate frequency in mhz
-* `set_jitter_chance_pc`: set jitter chance in percentage (0 - 100)
-  * 0: do not add any jitter
-  * 100: add jitter on every clock edge
-* `set_max_jitter_ps`: set maximum jitter in ps
-Following are `drive / sample` methods of `pins_if`:
-* `wait_for_reset`: wait for rst_n to assert and then deassert
-* `apply_reset`: apply reset with specified scheme out of following:
-  * fullly synchronous reset
-  * async assert, sync dessert
-  * async assert, async dessert
-  * clk gated when reset asserted
-* `add_jitter`: add jitter to `clk_hi` and `clk_lo` half periods based on
-  `jitter_chance_pc`
-* `start_clk`: start / ungate clock
+
+Unlike `clk_if`, this interface can generate a clock and a reset signal. These
+are connected as `inout` signals and the interface observes them passively
+unless the `set_active` function is called.
+
+Just like `clk_if`, this interface has clocking blocks `cb` and `cbn`, together
+with `wait_clks` and `wait_n_clks` utility tasks. It also has
+* `wait_for_reset`: wait for a reset signalled on `rst_n`
+
+To generate a clock signal, call `set_active` at the start of the simulation.
+This is typically called from an `initial` block in the testbench. To configure
+the frequency and duty cycle of the generated clock, use the following
+functions:
+* `set_freq_mhz` / `set_freq_khz`: set the clock frequency in MHz / KHz. This
+  is 50MHz by default.
+* `set_period_ns`: set the clock period in nanoseconds. This is 20ns by default
+  (giving a clock period of 50MHz).
+* `set_duty_cycle`: set the duty cycle (as a percentage: 1 - 99). This is 50 by
+  default.
+
+The clock can also have jitter added. This is generated as an offset in
+picoseconds added to randomly selected clock half-periods. It can be enabled
+and configured with:
+* `set_jitter_chance_pc`: set the percentage probability of adding a jitter to
+  a given half-period. By default, this is 0 and the clock has no jitter.
+* `set_max_jitter_ps`: set the maximum jitter to add to each clock half-period
+  in picoseconds. This is 1000ps (1 ns) by default.
+
+To start and stop the clock or apply a reset, use the following tasks. These
+will have no effect if `set_active` has not been called.
+* `start_clk`: start the clock. The clock is started by default, so this
+  task is only needed after a call to `stop_clk`.
 * `stop_clk`: stop / gate the clk
-* `wait_clks`: waits for specified number of positive clock edges
-* `wait_n_clks`: waits for specified number of negative clock edges
+* `apply_reset`: signal a reset on `rst_n`. The length of this reset and
+  whether it is synchronous or not can be configured with arguments to the
+  function.
 
 ### `pins_if`
-This paramterized interface provides the ability to drive / sample any signal
+
+This parameterized interface provides the ability to drive or sample any signal
 in the DUT.
+
 ```systemverilog
 interface pins_if #(
   parameter int Width = 1
 ) (
   inout [Width-1:0] pins
 );
 ```
-The member `pins` is inout type and it can be connected to any of input or
-output port within of dut to drive or sample them. `pins` can be driven either
-internally using `pins_o` and `pins_oe` signals, that constitute a tri-state
-buffer implementation. This provide an ability to disconnects `pins` by driving
-them to high impedance state. `pins` may also be driven through an external
-driver that it gets connected to. This interface also provides capability
-to drive weak pull-up or pull-down on `pins` in case of no internal or external
-drivers. The members `pins_pu` and `pins_pd` control weak pull-up or pull-down
-functionality. Following diagram explains working of `pins_if`:
-
-## `pins_if` block diagram
-![Block diagram](pins_if.svg)
 
-Some of the commonly used methods of `pins_if` are as follows:
-* `drive_en_pin`: Drive specified value `val` on specified index `idx` of
-  `pins_oe` signal
-* `drive_en`: Drive `pins_oe` signal to specified value `val`
-* `drive_pin`: Drive specified index `idx` of pins_oe signal to 1, and the same
-  index of `pins_o` to specified value `val`
-  value
-* `drive`: Drive `pins_oe` to all 1's and specified value `val` on `pins_o`
-* `sample_pin`: Sample and return value of `pins[idx]` for specified index `idx`
-* `sample`: Sample and return value of `pins`
-* `set_pullup_en`: Implement pull-up on specific bits of `pins` based on
-  specified value `val`
-* `set_pulldown_en`: Implement pull-down on specifc bits of `pins` based on
-  specified value `val`
+By default, it behaves as a passive interface. The values of the pins can be
+read with the following functions:
+* `sample`: sample and return all the pin values
+* `sample_pin`: sample just the given pin
+
+The interface can also be configured to drive, pull up, or pull down its
+outputs. To do this, call
+* `drive` / `drive_pin`: Drive the output to the given value.
+* `drive_en` / `drive_en_pin`: Configure output enable; when enabled, this
+  drives value previously stored by a call to `drive` or `drive_pin`.
+* `set_pullup_en` / `set_pullup_en_pin`: Configure pull-up setting. If true and
+  output enable is false, drives the output to `1`.
+* `set_pulldown_en` / `set_pulldown_en_pin`: Configure pull-down setting. If
+  true and both output_enable and pull-up are false, drives the output to `0`.
+
+The diagram below gives a schematic view of `pins_if`. The driver shown is
+replicated for each bit.
+
+![Block diagram](pins_if.svg)
diff --git a/vendor/lowrisc_ip/dv/sv/common_ifs/pins_if.sv b/vendor/lowrisc_ip/dv/sv/common_ifs/pins_if.sv
@@ -15,7 +15,6 @@ interface pins_if #(
 
 
   logic [Width-1:0] pins_o;       // value to be driven out
-  wire  [Width-1:0] pins_int;     // value of pin using internal pull-up / pull-down
   bit   [Width-1:0] pins_oe = '0; // output enable
   bit   [Width-1:0] pins_pd = '0; // pull down enable
   bit   [Width-1:0] pins_pu = '0; // pull up enable
@@ -73,24 +72,26 @@ interface pins_if #(
   endfunction
 
   // make connections
-  generate
-    for (genvar i = 0; i < Width; i++) begin : each_pin
-      assign pins_int[i] = pins_pd[i] ? 1'b0 :
-                           pins_pu[i] ? 1'b1 : 1'bz;
-      // If output enable is 1, strong driver assigns pin to 'value to be driven out';
-      // the external strong driver can still affect pin, if exists.
-      // Else if output enable is 0, weak pullup or pulldown is applied to pin.
-      // By doing this, we make sure that weak pullup or pulldown does not override
-      // any 'x' value on pin, that may result due to conflicting values
-      // between 'value to be driven out' and the external driver's value.
-      assign pins[i] = pins_oe[i] ? pins_o[i] : 1'bz;
+  for (genvar i = 0; i < Width; i++) begin : each_pin
 `ifdef VERILATOR
-      assign pins[i] = ~pins_oe[i] ? pins_int[i] : 1'bz;
+    assign pins[i] = pins_oe[i] ? pins_o[i] :
+                     pins_pu[i] ? 1'b1 :
+                     pins_pd[i] ? 1'b0 : 1'bz;
 `else
-      assign (pull0, pull1) pins[i] = ~pins_oe[i] ? pins_int[i] : 1'bz;
+    // Drive the pin with pull strength based on whether pullup / pulldown is enabled.
+    assign (pull0, pull1) pins[i] = ~pins_oe[i] ? (pins_pu[i] ? 1'b1 :
+                                                   pins_pd[i] ? 1'b0 : 1'bz) : 1'bz;
+
+
+    // If output enable is 1, strong driver assigns pin to 'value to be driven out';
+    // the external strong driver can still affect pin, if exists.
+    // Else if output enable is 0, weak pullup or pulldown is applied to pin.
+    // By doing this, we make sure that weak pullup or pulldown does not override
+    // any 'x' value on pin, that may result due to conflicting values
+    // between 'value to be driven out' and the external driver's value.
+    assign pins[i] = pins_oe[i] ? pins_o[i] : 1'bz;
 `endif
-    end
-  endgenerate
+  end
 
 endinterface
 `endif
diff --git a/vendor/lowrisc_ip/dv/sv/common_ifs/pins_if.svg b/vendor/lowrisc_ip/dv/sv/common_ifs/pins_if.svg
diff --git a/vendor/lowrisc_ip/dv/sv/csr_utils/README.md b/vendor/lowrisc_ip/dv/sv/csr_utils/README.md
@@ -123,7 +123,7 @@ Supported CSR test sequences are:
    the read results with the expected values
 
 ### CSR exclusion methodology
-The CSR test sequences listed above intend to perform a sanity check to CSR
+The CSR test sequences listed above intend to perform a basic check to CSR
 read/write accesses, but do not intend to check specific DUT functionalities. Thus the
 sequences might need to exclude reading or writing certain CSRs depending on the
 specific testbench.

diff --git a/vendor/lowrisc_ip/dv/sv/csr_utils/csr_seq_lib.sv b/vendor/lowrisc_ip/dv/sv/csr_utils/csr_seq_lib.sv
@@ -219,14 +219,6 @@ class csr_rw_seq extends csr_base_seq;
 
   `uvm_object_new
 
-  rand bit do_csr_rd_check;
-  rand bit do_csr_field_rd_check;
-
-  constraint csr_or_field_rd_check_c {
-    // at least one of them should be set
-    do_csr_rd_check || do_csr_field_rd_check;
-  }
-
   virtual task body();
     foreach (test_csrs[i]) begin
       uvm_reg_data_t wdata;
@@ -243,7 +235,6 @@ class csr_rw_seq extends csr_base_seq;
       `uvm_info(`gtn, $sformatf("Verifying register read/write for %0s",
                                 test_csrs[i].get_full_name()), UVM_MEDIUM)
 
-      `DV_CHECK_FATAL(randomize(do_csr_rd_check, do_csr_field_rd_check))
       `DV_CHECK_STD_RANDOMIZE_FATAL(wdata)
       wdata &= get_mask_excl_fields(test_csrs[i], CsrExclWrite, CsrRwTest, m_csr_excl_item);
 
@@ -254,33 +245,14 @@ class csr_rw_seq extends csr_base_seq;
       // register is getting the updated access information.
       csr_wr(.csr(test_csrs[i]), .value(wdata), .blocking(0), .predict(!external_checker));
 
-      // check if parent block or register is excluded from read-check
-      if (m_csr_excl_item.is_excl(test_csrs[i], CsrExclWriteCheck, CsrRwTest)) begin
-        `uvm_info(`gtn, $sformatf("Skipping register %0s due to CsrExclWriteCheck exclusion",
-                                  test_csrs[i].get_full_name()), UVM_MEDIUM)
-        continue;
-      end
+      do_check_csr_or_field_rd(.csr(test_csrs[i]),
+                              .blocking(0),
+                              .compare(!external_checker),
+                              .compare_vs_ral(1),
+                              .csr_excl_type(CsrExclWriteCheck),
+                              .csr_test_type(CsrRwTest),
+                              .csr_excl_item(m_csr_excl_item));
 
-      compare_mask = get_mask_excl_fields(test_csrs[i], CsrExclWriteCheck, CsrRwTest,
-                                          m_csr_excl_item);
-      if (do_csr_rd_check) begin
-        csr_rd_check(.ptr           (test_csrs[i]),
-                     .blocking      (0),
-                     .compare       (!external_checker),
-                     .compare_vs_ral(1'b1),
-                     .compare_mask  (compare_mask));
-      end
-      if (do_csr_field_rd_check) begin
-        test_csrs[i].get_fields(test_fields);
-        test_fields.shuffle();
-        foreach (test_fields[j]) begin
-          bit compare = !m_csr_excl_item.is_excl(test_fields[j], CsrExclWriteCheck, CsrRwTest);
-          csr_rd_check(.ptr           (test_fields[j]),
-                       .blocking      (0),
-                       .compare       (!external_checker && compare),
-                       .compare_vs_ral(1'b1));
-        end
-      end
       wait_if_max_outstanding_accesses_reached();
     end
   endtask
@@ -392,14 +364,7 @@ class csr_bit_bash_seq extends csr_base_seq;
       val = rg.get();
       val[k]  = ~val[k];
       err_msg = $sformatf("Wrote %0s[%0d]: %0b", rg.get_full_name(), k, val[k]);
-      csr_wr(.csr(rg), .value(val), .blocking(1));
-
-      // if external checker is not enabled and writes are made non-blocking, then we need to
-      // pre-predict so that the mirrored value will be updated. if we dont, then csr_rd_check task
-      // might pick up stale mirrored value
-      if (!external_checker) begin
-        void'(rg.predict(.value(val), .kind(UVM_PREDICT_WRITE)));
-      end
+      csr_wr(.csr(rg), .value(val), .blocking(1), .predict(!external_checker));
 
       // TODO, outstanding access to same reg isn't supported in uvm_reg. Need to add another seq
       // uvm_reg waits until transaction is completed, before start another read/write in same reg
@@ -442,14 +407,7 @@ class csr_aliasing_seq extends csr_base_seq;
 
       `DV_CHECK_STD_RANDOMIZE_FATAL(wdata)
       wdata &= get_mask_excl_fields(test_csrs[i], CsrExclWrite, CsrAliasingTest, m_csr_excl_item);
-      csr_wr(.csr(test_csrs[i]), .value(wdata), .blocking(0));
-
-      // if external checker is not enabled and writes are made non-blocking, then we need to
-      // pre-predict so that the mirrored value will be updated. if we dont, then csr_rd_check task
-      // might pick up stale mirrored value
-      if (!external_checker) begin
-        void'(test_csrs[i].predict(.value(wdata), .kind(UVM_PREDICT_WRITE)));
-      end
+      csr_wr(.csr(test_csrs[i]), .value(wdata), .blocking(0), .predict(!external_checker));
 
       all_csrs.shuffle();
       foreach (all_csrs[j]) begin