Correct clock dfivider change and remove 7-seg constraints

lowRISC · Apr 6, 2017 · 9e4db4c · 9e4db4c
1 parent 38b28bb
commit 9e4db4c
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Showing 3 changed files with 50 additions and 37 deletions.
diff --git a/verilog/minion_soc.sv b/verilog/minion_soc.sv
@@ -373,7 +373,7 @@ always @(posedge msoc_clk or negedge rstn)
 	sd_blkcnt_reg <= 0;
 	sd_blksize_reg <= 0;
 	sd_data_start_reg <= 0;
-	clock_divider_sd_clk <= 0;
+	clock_divider_sd_clk_reg <= 0;
 	sd_cmd_i_reg <= 0;
 	sd_cmd_arg_reg <= 0;
 	sd_cmd_setting_reg <= 0;

diff --git a/vivado/srcs/onboard_qspi.xdc b/vivado/srcs/onboard_qspi.xdc
@@ -0,0 +1,49 @@
+# Flash/SPI Pins
+set_property PACKAGE_PIN L13 [get_ports flash_ss]
+set_property IOSTANDARD LVCMOS33 [get_ports flash_ss]
+set_property PACKAGE_PIN K17 [get_ports {flash_io[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {flash_io[0]}]
+set_property PACKAGE_PIN K18 [get_ports {flash_io[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {flash_io[1]}]
+set_property PACKAGE_PIN L14 [get_ports {flash_io[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {flash_io[2]}]
+set_property PACKAGE_PIN M14 [get_ports {flash_io[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {flash_io[3]}]
+#
+##7 segment display
+
+set_property PACKAGE_PIN T10 [get_ports {SEG[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SEG[0]}]
+set_property PACKAGE_PIN R10 [get_ports {SEG[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SEG[1]}]
+set_property PACKAGE_PIN K16 [get_ports {SEG[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SEG[2]}]
+set_property PACKAGE_PIN K13 [get_ports {SEG[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SEG[3]}]
+set_property PACKAGE_PIN P15 [get_ports {SEG[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SEG[4]}]
+set_property PACKAGE_PIN T11 [get_ports {SEG[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SEG[5]}]
+set_property PACKAGE_PIN L18 [get_ports {SEG[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SEG[6]}]
+
+set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports DP]
+
+set_property PACKAGE_PIN J17 [get_ports {AN[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {AN[0]}]
+set_property PACKAGE_PIN J18 [get_ports {AN[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {AN[1]}]
+set_property PACKAGE_PIN T9 [get_ports {AN[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {AN[2]}]
+set_property PACKAGE_PIN J14 [get_ports {AN[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {AN[3]}]
+set_property PACKAGE_PIN P14 [get_ports {AN[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {AN[4]}]
+set_property PACKAGE_PIN T14 [get_ports {AN[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {AN[5]}]
+set_property PACKAGE_PIN K2 [get_ports {AN[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {AN[6]}]
+set_property PACKAGE_PIN U13 [get_ports {AN[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {AN[7]}]
+
+#set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
diff --git a/vivado/srcs/video_keyboard_io_nexys4ddr.xdc b/vivado/srcs/video_keyboard_io_nexys4ddr.xdc
@@ -1,39 +1,3 @@
-##7 segment display
-
-set_property PACKAGE_PIN T10 [get_ports {SEG[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {SEG[0]}]
-set_property PACKAGE_PIN R10 [get_ports {SEG[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {SEG[1]}]
-set_property PACKAGE_PIN K16 [get_ports {SEG[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {SEG[2]}]
-set_property PACKAGE_PIN K13 [get_ports {SEG[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {SEG[3]}]
-set_property PACKAGE_PIN P15 [get_ports {SEG[4]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {SEG[4]}]
-set_property PACKAGE_PIN T11 [get_ports {SEG[5]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {SEG[5]}]
-set_property PACKAGE_PIN L18 [get_ports {SEG[6]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {SEG[6]}]
-
-set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports DP]
-
-set_property PACKAGE_PIN J17 [get_ports {AN[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {AN[0]}]
-set_property PACKAGE_PIN J18 [get_ports {AN[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {AN[1]}]
-set_property PACKAGE_PIN T9 [get_ports {AN[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {AN[2]}]
-set_property PACKAGE_PIN J14 [get_ports {AN[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {AN[3]}]
-set_property PACKAGE_PIN P14 [get_ports {AN[4]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {AN[4]}]
-set_property PACKAGE_PIN T14 [get_ports {AN[5]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {AN[5]}]
-set_property PACKAGE_PIN K2 [get_ports {AN[6]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {AN[6]}]
-set_property PACKAGE_PIN U13 [get_ports {AN[7]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {AN[7]}]
-
 
 ##Buttons
 set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports GPIO_SW_C]