[tlul,rtl] Rework tlul_err_resp

Previously the logic of tlul_err_resp was more complex than was required
(having seperate flops for tracking a pending request and response where
it's sufficient to just track a pending response).

This simplifies the logic and cuts a path from the incoming data ready
to the outgoing address ready.

Signed-off-by: Greg Chadwick <gac@lowrisc.org>

hw/ip/tlul/rtl/tlul_err_resp.sv

@@ -18,7 +18,7 @@ module tlul_err_resp (
   tl_a_op_e                          err_opcode;
   logic [$bits(tl_h_i.a_source)-1:0] err_source;
   logic [$bits(tl_h_i.a_size)-1:0]   err_size;
-  logic                              err_req_pending, err_rsp_pending;
+  logic                              err_rsp_pending;
   mubi4_t                            err_instr_type;
   tlul_pkg::tl_d2h_t                 tl_h_o_int;
 
@@ -32,24 +32,24 @@ module tlul_err_resp (
 
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
-      err_req_pending <= 1'b0;
+      err_rsp_pending <= 1'b0;
       err_source      <= {top_pkg::TL_AIW{1'b0}};
       err_opcode      <= Get;
       err_size        <= '0;
       err_instr_type  <= MuBi4False;
+    end else if(err_rsp_pending && tl_h_i.d_ready) begin
+      err_rsp_pending <= 1'b0;
     end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
-      err_req_pending <= 1'b1;
+      err_rsp_pending <= 1'b1;
       err_source      <= tl_h_i.a_source;
       err_opcode      <= tl_h_i.a_opcode;
       err_size        <= tl_h_i.a_size;
       err_instr_type  <= tl_h_i.a_user.instr_type;
-    end else if (!err_rsp_pending) begin
-      err_req_pending <= 1'b0;
     end
   end
 
-  assign tl_h_o_int.a_ready  = ~err_rsp_pending & ~(err_req_pending & ~tl_h_i.d_ready);
-  assign tl_h_o_int.d_valid  = err_req_pending | err_rsp_pending;
+  assign tl_h_o_int.a_ready  = ~err_rsp_pending;
+  assign tl_h_o_int.d_valid  = err_rsp_pending;
   assign tl_h_o_int.d_data   = (mubi4_test_true_strict(err_instr_type)) ? DataWhenInstrError :
                                                                           DataWhenError;
   assign tl_h_o_int.d_source = err_source;
@@ -60,16 +60,6 @@ module tlul_err_resp (
   assign tl_h_o_int.d_user   = '0;
   assign tl_h_o_int.d_error  = 1'b1;
 
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      err_rsp_pending <= 1'b0;
-    end else if ((err_req_pending || err_rsp_pending) && !tl_h_i.d_ready) begin
-      err_rsp_pending <= 1'b1;
-    end else begin
-      err_rsp_pending <= 1'b0;
-    end
-  end
-
   // Waive unused bits of tl_h_i
   logic unused_tl_h;
   assign unused_tl_h = ^tl_h_i;