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Fix OTP splicing with updatemem #15162

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dmcardle opened this issue Sep 27, 2022 · 5 comments · Fixed by #15163
Closed

Fix OTP splicing with updatemem #15162

dmcardle opened this issue Sep 27, 2022 · 5 comments · Fixed by #15163
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Component:FPGA FPGA related issues Type:Bug Bugs
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@dmcardle
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I think OTP splicing might not be working properly. I changed the value of CREATOR_SW_CFG_ROM_EXEC_EN and modified the SRAM execution test to (1) use an OTP-spliced bitstream and (2) print the OTP value at the expected address. Bazel definitely ran the commands to splice the OTP image in, but when the GDB script ran, it printed the default value for CREATOR_SW_CFG_ROM_EXEC_EN rather than the value I chose.

I believe these local changes are sufficient to reproduce the result when running ./bazelisk.sh test --define bitstream=gcp_splice //sw/device/examples/sram_program:sram_program_fpga_cw310_test. (The SRAM program test was just handy, but it should be irrelevant because GDB is printing the value before loading the SRAM program into memory.)

diff --git a/rules/otp.bzl b/rules/otp.bzl
index cfc36daca..0a16f4413 100644
--- a/rules/otp.bzl
+++ b/rules/otp.bzl
@@ -38,7 +38,8 @@ def _otp_json_impl(ctx):
                 "CREATOR_SW_CFG_RNG_EN": "0x739",
                 # ROM execution is enabled if this item is set to a non-zero
                 # value.
-                "CREATOR_SW_CFG_ROM_EXEC_EN": "0xffffffff",
+                #"CREATOR_SW_CFG_ROM_EXEC_EN": "0xffffffff",
+                "CREATOR_SW_CFG_ROM_EXEC_EN": "0x11235813",
                 # Value to write to the cpuctrl CSR in `rom_init()`.
                 # See:
                 # https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html#cpu-control-register-cpuctrl
diff --git a/sw/device/examples/sram_program/BUILD b/sw/device/examples/sram_program/BUILD
index bbe7f68a1..eb742fb03 100644
--- a/sw/device/examples/sram_program/BUILD
+++ b/sw/device/examples/sram_program/BUILD
@@ -106,6 +106,9 @@ opentitan_gdb_fpga_cw310_test(
         monitor reg pmpcfg0 0x9f9f9f9f
         monitor reg pmpaddr0 0x7fffffff

+        echo :::: Value of CREATOR_SW_CFG_ROM_EXEC_EN.\\n
+        monitor mdw 0x40131108
+
         echo :::: Load the SRAM program onto the device and check integrity.\\n
         file sram_program.elf
         load sram_program.elf
@@ -125,7 +128,7 @@ opentitan_gdb_fpga_cw310_test(
         ":sram_program_fpga_cw310.elf": "sram_program.elf",
         "//sw/device/silicon_creator/rom:rom_fpga_cw310.elf": "rom.elf",
     },
-    rom_bitstream = "//hw/bitstream:rom",
+    rom_bitstream = "//hw/bitstream:rom_otp_dev",
     rom_kind = "Rom",
     tags = [

Let's peek at the MMI files that we generated with vivado_hook_write_bitstream_pre.tcl.

I noticed a few things:

  1. The DataWidth values in rom.mmi do not overlap, but the ones in otp.mmi do overlap. I think this is forbidden per the Xilinx updatemem manual:

    There cannot be any gaps or overlaps in bit-lane numbering. All bit-lanes in an Address Block must be the same number of bits wide.

    I wonder whether this has something to do with the TCL condition that adds 3 to the slice_end variable. vivado_hook_write_bitstream_pre.tcl:66

  2. The Placement values in rom.mmi are of the form "X{}Y{}" like the updatemem manual examples, but the values in otp.mmi are prefixed with 18_.
    I have a suspicion that we're not trimming the right string from the left of the LOC property for OTP images. vivado_hook_write_bitstream_pre.tcl:60

rom.mmi

<?xml version="1.0" encoding="UTF-8"?>
<MemInfo Version="1" Minor="0">
  <Processor Endianness="Little" InstPath="dummy">
  <AddressSpace Name="rom" Begin="0" End="81919">
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X6Y33">
          <DataWidth MSB="3" LSB="0"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB32" Placement="X5Y33">
          <DataWidth MSB="7" LSB="4"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB32" Placement="X5Y35">
          <DataWidth MSB="11" LSB="8"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
...

otp.mmi

<?xml version="1.0" encoding="UTF-8"?>
<MemInfo Version="1" Minor="0">
  <Processor Endianness="Little" InstPath="dummy">
  <AddressSpace Name="rom" Begin="0" End="22527">
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="18_X7Y112">
          <DataWidth MSB="3" LSB="0"/>
          <AddressRange Begin="0" End="1023"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB32" Placement="18_X7Y120">
          <DataWidth MSB="4" LSB="1"/>
          <AddressRange Begin="0" End="1023"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB32" Placement="18_X8Y123">
          <DataWidth MSB="5" LSB="2"/>
          <AddressRange Begin="0" End="1023"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
@dmcardle dmcardle added Component:FPGA FPGA related issues Type:Bug Bugs labels Sep 27, 2022
@dmcardle dmcardle added this to the Project: M2 milestone Sep 27, 2022
@dmcardle dmcardle self-assigned this Sep 27, 2022
@dmcardle
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I ran Vivado with a modified TCL script where I don't make modification to slice_end. At least superficially, rom.mmi looks unchanged, and otp.mmi doesn't appear to overlap anymore! (Still need to try the spliced bitstream on an FPGA.)

I opened the Vivado GUI and searched for cells of type BMEM.BRAM, and it's now very clear why the placement values have that strange prefix. For example, the OTP cell mem_reg_9 has a LOC value of RAMB18_X8Y126, so of course trimming RAMB36_ doesn't work quite right. I think I'll change the LOC trimming code to support both.

rom.mmi

<?xml version="1.0" encoding="UTF-8"?>
<MemInfo Version="1" Minor="0">
  <Processor Endianness="Little" InstPath="dummy">
  <AddressSpace Name="rom" Begin="0" End="39935">
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X7Y35">
          <DataWidth MSB="3" LSB="0"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB32" Placement="X6Y37">
          <DataWidth MSB="7" LSB="4"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB32" Placement="X7Y39">
          <DataWidth MSB="11" LSB="8"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>

otp.mmi

<?xml version="1.0" encoding="UTF-8"?>
<MemInfo Version="1" Minor="0">
  <Processor Endianness="Little" InstPath="dummy">
  <AddressSpace Name="rom" Begin="0" End="2815">
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="18_X8Y127">
          <DataWidth MSB="0" LSB="0"/>
          <AddressRange Begin="0" End="1023"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB32" Placement="18_X7Y125">
          <DataWidth MSB="1" LSB="1"/>
          <AddressRange Begin="0" End="1023"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB32" Placement="18_X7Y123">
          <DataWidth MSB="2" LSB="2"/>
          <AddressRange Begin="0" End="1023"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>

dmcardle added a commit to dmcardle/opentitan that referenced this issue Sep 27, 2022
Signed-off-by: Dan McArdle <dmcardle@google.com>
@dmcardle
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dmcardle commented Oct 5, 2022

To summarize, I think the root of this issue is that the MMI file(s) we generate are probably incorrect, causing updatemem to do some unwanted edit to our bitstream file.

Ideally, I would just call write_mem_info to generate an MMI file for the entire project. I've had no luck running the command in the Vivado GUI — it just says that the file could not be written. It's not a filesystem permission issue, and the -verbose flag didn't add any new messages. I tried strace which showed it was successfully opening the mmi file, then closing and deleting it.

I do wonder whether I was running write_mem_info in the appropriate environment. I opened the implemented design and went straight to the TCL console. I wonder whether it would be better if we actually ran it before writing the bitstream, at the step named STEPS.WRITE_BITSTREAM.TCL.PRE. (Aside: I noticed that our vivado_hook_write_bitstream_pre.tcl script is actually not running at this stage per this comment.)

I have a few things to try:

  • I'm currently running a build that will call manually invoke write_bitstream with some new flags.
    • -raw_bitfile is supposed to generate an ASCII variant of the bitfile. I'm not holding my breath on this, though. I think it might just be a fixed-size header at the beginning of the file followed by a hexdump of the .bit file.
    • -logic_location_file says it generates a file containing bitstream positions of Block RAMs. This sounds promising — if all else fails, it might be worth trying to write our own updatemem.
  • I'd like to try generating MMI files with write_mem_info in a newer version of Vivado, if possible.

@dmcardle
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dmcardle commented Oct 5, 2022

One thing I don't quite understand is that the BRAMs for ROM appear to be "RAMB36", yet we write "RAMB32" into the MMI file. Our OTP BRAMs are "RAMB18", so it's not clear what memory type to claim in the MMI file. Some folks on a forum 5 years ago say that updatemem does not support RAMB18, but it's not a conclusive answer from Xilinx. I briefly tried enabling RAMB18 support with the effectively undocumented UPDATEMEM_ALLOW_RAMB18 environment variable but it didn't have the desired effect (sorry to be vague, I should have taken better notes.)

@dmcardle
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dmcardle commented Oct 5, 2022

As suspected, the file from -raw_bitfile is not so useful. It contains a flat header and then, apparently, the contents of the bit file encoded as ASCII zeroes and ones.

Created by Bitstream 2020.2 SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
Design name:    chip_earlgrey_cw310;UserID=0XFFFFFFFF;Version=2020.2
Architecture:   kintex7
Part:           7k410tfbg676
Date:           Wed Oct 05 11:46:49 2022
Bits:           127023328
11111111111111111111111111111111
11111111111111111111111111111111
11111111111111111111111111111111
11111111111111111111111111111111
11111111111111111111111111111111
11111111111111111111111111111111
11111111111111111111111111111111
11111111111111111111111111111111
00000000000000000000000010111011
00010001001000100000000001000100
11111111111111111111111111111111
11111111111111111111111111111111
10101010100110010101010101100110
00100000000000000000000000000000
00110000000000100010000000000001
00000000000000000000000000000000
00110000000000100000000000000001

The file from logic_location_file looks more promising if we were going to try to manually splice data into the bitstream.

Revision 3
; Created by bitgen 2020.2 at Wed Oct  5 11:47:04 2022
; Bit lines have the following form:
; <offset> <frame address> <frame offset> <information>
; <information> may be zero or more <kw>=<value> pairs
; Block=<blockname     specifies the block associated with this
;                      memory cell.
;
; Latch=<name>         specifies the latch associated with this memory cell.
;
; Net=<netname>        specifies the user net associated with this
;                      memory cell.
;
; COMPARE=[YES | NO]   specifies whether or not it is appropriate
;                      to compare this bit position between a
;                      "program" and a "readback" bitstream.
;                      If not present the default is NO.
;
; Ram=<ram id>:<bit>   This is used in cases where a CLB function
; Rom=<ram id>:<bit>   generator is used as RAM (or ROM).  <Ram id>
;                      will be either 'F', 'G', or 'M', indicating
;                      that it is part of a single F or G function
;                      generator used as RAM, or as a single RAM
;                      (or ROM) built from both F and G.  <Bit> is
;                      a decimal number.
;
; Info lines have the following form:
; Info <name>=<value>  specifies a bit associated with the LCA
;                      configuration options, and the value of
;                      that bit.  The names of these bits may have
;                      special meaning to software reading the .ll file.
;
Info STARTSEL0=1
Bit 92380387 0x0044371f    131 Block=SLICE_X170Y2 Latch=AQ Net=top_earlgrey/u_flash_ctrl/u_eflash/gen_flash_cores[0].u_core/u_scramble/gen_gf_mult.u_mult/gen_decomposed.prod_q_reg[63]_0[14]
Bit 90596388 0x00442f1f    196 Block=SLICE_X145Y3 Latch=AQ Net=top_earlgrey/u_flash_ctrl/u_eflash/gen_flash_cores[1].u_core/u_scramble/gen_gf_mult.u_mult/gen_decomposed.prod_q_reg[63]_0[23]
Bit 92380390 0x0044371f    134 Block=SLICE_X170Y2 Latch=A5FF.Q Net=top_earlgrey/u_flash_ctrl/u_eflash/gen_flash_cores[0].u_core/u_scramble/gen_gf_mult.u_mult/gen_decomposed.prod_q_reg[63]_0[15]
Bit 88838307 0x0044271f    323 Block=SLICE_X120Y5 Latch=AQ Net=top_earlgrey/u_flash_ctrl/u_eflash/u_flash/gen_generic.u_impl_generic/gen_prim_flash_banks[0].u_prim_flash_bank/rd_data_q[27]
Bit 90596389 0x00442f1f    197 Block=SLICE_X145Y3 Latch=A5FF.Q Net=top_earlgrey/u_flash_ctrl/u_eflash/gen_flash_cores[1].u_core/u_scramble/gen_gf_mult.u_mult/gen_decomposed.prod_q_reg[63]_0[24]
Bit 88838308 0x0044271f    324 Block=SLICE_X121Y5 Latch=AQ Net=top_earlgrey/u_flash_ctrl/u_eflash/u_flash/gen_generic.u_impl_generic/gen_prim_flash_banks[0].u_prim_flash_bank/u_cmd_fifo/gen_normal_fifo.storage_reg[1]_363[27]
Bit 88838332 0x0044271f    348 Block=SLICE_X120Y5 Latch=BQ Net=top_earlgrey/u_flash_ctrl/u_eflash/u_flash/gen_generic.u_impl_generic/gen_prim_flash_banks[0].u_prim_flash_bank/rd_data_q[29]
Bit 88838372 0x0044271f    388 Block=SLICE_X121Y6 Latch=AQ Net=top_earlgrey/u_flash_ctrl/u_flash_hw_if/rand_addr_key_o_reg[111]_0[11]

Filtering just the relevant stuff:

% grep -E 'u_otp_ctrl\/u_otp\/gen_generic\.u_impl_generic\/u_prim_ram_1p_adv\/' ~/tmp/vivado/dmcardle_bitstream_stuff.ll
Bit 31573668 0x0004179f    260 Block=SLICE_X73Y254 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[6]
Bit 31690019 0x0004181f    259 Block=SLICE_X74Y254 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[0]
Bit 31690044 0x0004181f    284 Block=SLICE_X74Y254 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[1]
Bit 31690083 0x0004181f    323 Block=SLICE_X74Y255 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[4]
Bit 31690084 0x0004181f    324 Block=SLICE_X75Y255 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[11]
Bit 31690108 0x0004181f    348 Block=SLICE_X74Y255 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[5]
Bit 31690109 0x0004181f    349 Block=SLICE_X75Y255 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[13]
Bit 31690114 0x0004181f    354 Block=SLICE_X75Y255 Latch=CQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[15]
Bit 31690139 0x0004181f    379 Block=SLICE_X75Y255 Latch=DQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[8]
Bit 31806435 0x0004189f    323 Block=SLICE_X76Y255 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[21]
Bit 31922723 0x0004191f    259 Block=SLICE_X78Y254 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[3]
Bit 31922788 0x0004191f    324 Block=SLICE_X79Y255 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[12]
Bit 31922812 0x0004191f    348 Block=SLICE_X78Y255 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[14]
Bit 31922813 0x0004191f    349 Block=SLICE_X79Y255 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[7]
Bit 31922817 0x0004191f    353 Block=SLICE_X78Y255 Latch=CQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[2]
Bit 32039139 0x0004199f    323 Block=SLICE_X80Y255 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[10]
Bit 32039164 0x0004199f    348 Block=SLICE_X80Y255 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[9]
Bit 32039331 0x0004199f    515 Block=SLICE_X80Y258 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[16]
Bit 32039356 0x0004199f    540 Block=SLICE_X80Y258 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[17]
Bit 32039361 0x0004199f    545 Block=SLICE_X80Y258 Latch=CQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[18]
Bit 32039386 0x0004199f    570 Block=SLICE_X80Y258 Latch=DQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[20]
Bit 32039715 0x0004199f    899 Block=SLICE_X80Y264 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rvalid
Bit 32041210 0x0004199f   2394 Block=SLICE_X80Y286 Latch=DQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rvalid_sram_q
Bit 45155428 0x0006199f   1156 Block=SLICE_X81Y318 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[14]
Bit 45155453 0x0006199f   1181 Block=SLICE_X81Y318 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/syndrome_o1__2[17]
Bit 45155458 0x0006199f   1186 Block=SLICE_X81Y318 Latch=CQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/syndrome_o1__1[18]
Bit 45155483 0x0006199f   1211 Block=SLICE_X81Y318 Latch=DQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/syndrome_o1__0[19]
Bit 45155907 0x0006199f   1635 Block=SLICE_X80Y325 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/wmask_q[21]
Bit 45155932 0x0006199f   1660 Block=SLICE_X80Y325 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/syndrome_o1__3[16]
Bit 45155937 0x0006199f   1665 Block=SLICE_X80Y325 Latch=CQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[5]
Bit 45155962 0x0006199f   1690 Block=SLICE_X80Y325 Latch=DQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[8]
Bit 43137788 0x0006109f    284 Block=SLICE_X50Y304 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_output.rdata_q_reg_n_0_[21]
Bit 43254820 0x0006111f    964 Block=SLICE_X53Y315 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[6]
Bit 15674180 0x00020b1f   2212 Block=SLICE_X33Y234 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/req_q
Bit 15674205 0x00020b1f   2237 Block=SLICE_X33Y234 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/write_q
Bit 32246499 0x00041a9f    835 Block=SLICE_X82Y263 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/gen_regslice_input.wdata_q_reg_n_0_[19]
Bit 45361379 0x00061a9f    259 Block=SLICE_X82Y304 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[12]
Bit 45361699 0x00061a9f    579 Block=SLICE_X82Y309 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[7]
Bit 45361724 0x00061a9f    604 Block=SLICE_X82Y309 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[9]
Bit 45363331 0x00061a9f   2211 Block=SLICE_X82Y334 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[1]
Bit 45363356 0x00061a9f   2236 Block=SLICE_X82Y334 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/syndrome_o1[20]
Bit 45363361 0x00061a9f   2241 Block=SLICE_X82Y334 Latch=CQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[2]
Bit 45477860 0x00061b1f    388 Block=SLICE_X85Y306 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[10]
Bit 45477885 0x00061b1f    413 Block=SLICE_X85Y306 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[3]
Bit 30903875 0x0004149f   2723 Block=SLICE_X62Y292 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[0]
Bit 29467299 0x00040e1f   1155 Block=SLICE_X42Y268 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/addr_q[0]
Bit 29467324 0x00040e1f   1180 Block=SLICE_X42Y268 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/addr_q[1]
Bit 29467329 0x00040e1f   1185 Block=SLICE_X42Y268 Latch=CQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/addr_q[2]
Bit 29467354 0x00040e1f   1210 Block=SLICE_X42Y268 Latch=DQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/addr_q[3]
Bit 29467363 0x00040e1f   1219 Block=SLICE_X42Y269 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/addr_q[4]
Bit 29467388 0x00040e1f   1244 Block=SLICE_X42Y269 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/addr_q[5]
Bit 29467393 0x00040e1f   1249 Block=SLICE_X42Y269 Latch=CQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/addr_q[6]
Bit 29467418 0x00040e1f   1274 Block=SLICE_X42Y269 Latch=DQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/addr_q[7]
Bit 29467427 0x00040e1f   1283 Block=SLICE_X42Y270 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/addr_q[8]
Bit 29467452 0x00040e1f   1308 Block=SLICE_X42Y270 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/addr_q[9]
Bit 44340315 0x0006161f    507 Block=SLICE_X67Y307 Latch=DQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[13]
Bit 44340835 0x0006161f   1027 Block=SLICE_X66Y316 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[11]
Bit 44340860 0x0006161f   1052 Block=SLICE_X66Y316 Latch=BQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[15]
Bit 44341507 0x0006161f   1699 Block=SLICE_X66Y326 Latch=AQ Net=top_earlgrey/u_otp_ctrl/u_otp/gen_generic.u_impl_generic/u_prim_ram_1p_adv/rdata_ecc[4]

I think the first 22 lines of output correspond to the 22 BRAM cells, but I'm not exactly sure what to do with the <offset>, <frame address>, and <frame offset> values. I think that the frame address is a word number and the frame offset is a bit offset, but I'm surprised there's not another dimension for the depth.

@a-will
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a-will commented Oct 6, 2022

If you change the minor version of the file to 1, it looks like updatemem accepts the RAMB18:

<?xml version="1.0" encoding="UTF-8"?>
-<MemInfo Version="1" Minor="0">
+<MemInfo Version="1" Minor="1">
  <Processor Endianness="Little" InstPath="dummy">

dmcardle added a commit to dmcardle/opentitan that referenced this issue Oct 10, 2022
Signed-off-by: Dan McArdle <dmcardle@google.com>
dmcardle added a commit to dmcardle/opentitan that referenced this issue Oct 14, 2022
Signed-off-by: Dan McArdle <dmcardle@google.com>
dmcardle added a commit to dmcardle/opentitan that referenced this issue Oct 15, 2022
Signed-off-by: Dan McArdle <dmcardle@google.com>
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