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Fix OTP bitstream splicing #15163

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merged 5 commits into from
Oct 19, 2022
Merged

Fix OTP bitstream splicing #15163

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ad555b6
[fpga] Fix OTP-specific behavior in MMI file generator
dmcardle Oct 15, 2022
387b0fc
[fpga] Refactor quirks in MMI file generator
dmcardle Oct 18, 2022
1438c8c
[fpga] Add special case for OTP to gen_vivado_mem_image.py
dmcardle Oct 15, 2022
f758e67
[bazel] Add "exec_disabled" OTP image and refactor
dmcardle Oct 15, 2022
8f27d78
[sw] Disable ROM execution for sram_program_fpga_cw310_test
dmcardle Oct 15, 2022
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59 changes: 37 additions & 22 deletions hw/bitstream/BUILD
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
# SPDX-License-Identifier: Apache-2.0

load("//rules:splice.bzl", "bitstream_splice")
load("//rules:otp.bzl", "get_otp_images")

package(default_visibility = ["//visibility:public"])

Expand Down Expand Up @@ -60,6 +61,7 @@ filegroup(
"bitstream_gcp_splice": [":gcp_spliced_test_rom"],
"//conditions:default": ["@bitstreams//:bitstream_test_rom"],
}),
tags = ["manual"],
)

filegroup(
Expand All @@ -70,18 +72,7 @@ filegroup(
"bitstream_gcp_splice": [":gcp_spliced_rom"],
"//conditions:default": ["@bitstreams//:bitstream_rom"],
}),
)

filegroup(
name = "rom_otp_dev",
srcs = select({
"bitstream_skip": ["skip.bit"],
"bitstream_vivado": ["//hw/bitstream/vivado:fpga_cw310_rom_otp_dev"],
"bitstream_gcp_splice": [":gcp_spliced_rom_otp_dev"],
# FIXME(#13603) By default, this will actually do a local splice instead
# of retrieving the pre-spliced bitstream from the cache.
"//conditions:default": [":gcp_spliced_rom_otp_dev"],
}),
tags = ["manual"],
)

filegroup(
Expand All @@ -91,6 +82,7 @@ filegroup(
"bitstream_vivado": ["//hw/bitstream/vivado:rom_mmi"],
"//conditions:default": ["@bitstreams//:rom_mmi"],
}),
tags = ["manual"],
)

filegroup(
Expand All @@ -100,8 +92,28 @@ filegroup(
"bitstream_vivado": ["//hw/bitstream/vivado:otp_mmi"],
"//conditions:default": ["@bitstreams//:otp_mmi"],
}),
tags = ["manual"],
)

[
filegroup(
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Can you add a "manual" tag to these filegroups? That way, Vivado-dependent targets won't get picked up by wildcards.

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Done. I added to the other filegroups as well. I think that this hasn't been an issue because these targets aren't tests.

name = "rom_otp_" + otp_name,
srcs = select({
"bitstream_skip": ["skip.bit"],
"bitstream_vivado": ["//hw/bitstream/vivado:fpga_cw310_rom_otp_" + otp_name],
"bitstream_gcp_splice": [":gcp_spliced_rom_otp_" + otp_name],

# FIXME(#13807) By default, this will actually do a local splice
# instead of retrieving the pre-spliced bitstream from the cache.
# Before we cache OTP-spliced bitstreams, we need to work out the
# details of the naming scheme.
"//conditions:default": [":gcp_spliced_rom_otp_" + otp_name],
}),
tags = ["manual"],
)
for (otp_name, _) in get_otp_images()
]

# Build the Test ROM and splice it into a cached bitstream.
bitstream_splice(
name = "gcp_spliced_test_rom",
Expand All @@ -124,13 +136,16 @@ bitstream_splice(
visibility = ["//visibility:private"],
)

# Splice the OTP Dev image into `:gcp_spliced_rom`.
bitstream_splice(
name = "gcp_spliced_rom_otp_dev",
src = ":gcp_spliced_rom",
data = "//hw/ip/otp_ctrl/data:img_dev",
meminfo = ":otp_mmi",
tags = ["manual"],
update_usr_access = True,
visibility = ["//visibility:private"],
)
# Splice OTP images into the locally-spliced ROM bitstream.
[
bitstream_splice(
name = "gcp_spliced_rom_otp_" + otp_name,
src = ":gcp_spliced_rom",
data = img_target,
meminfo = ":otp_mmi",
tags = ["manual"],
update_usr_access = True,
visibility = ["//visibility:private"],
)
for (otp_name, img_target) in get_otp_images()
]
24 changes: 15 additions & 9 deletions hw/bitstream/vivado/BUILD
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@

load("@rules_pkg//pkg:mappings.bzl", "pkg_filegroup", "pkg_files")
load("//rules:fusesoc.bzl", "fusesoc_build")
load("//rules:otp.bzl", "get_otp_images")
load("//rules:splice.bzl", "bitstream_splice")

package(default_visibility = ["//visibility:public"])
Expand Down Expand Up @@ -80,14 +81,17 @@ bitstream_splice(
tags = ["manual"],
)

# Splice in the dev OTP image, replacing the RMA image.
bitstream_splice(
name = "fpga_cw310_rom_otp_dev",
src = ":fpga_cw310_rom",
data = "//hw/ip/otp_ctrl/data:img_dev",
meminfo = ":otp_mmi",
tags = ["manual"],
)
# Splice OTP images into the ROM bitstream.
[
bitstream_splice(
name = "fpga_cw310_rom_otp_" + otp_name,
src = ":fpga_cw310_rom",
data = img_target,
meminfo = ":otp_mmi",
tags = ["manual"],
)
for (otp_name, img_target) in get_otp_images()
]

# Standalone CW310 image for use with hyperdebug.
fusesoc_build(
Expand Down Expand Up @@ -139,10 +143,12 @@ pkg_files(
name = "standard",
srcs = [
":fpga_cw310_rom",
":fpga_cw310_rom_otp_dev",
":fpga_cw310_test_rom",
":otp_mmi",
":rom_mmi",
] + [
":fpga_cw310_rom_otp_" + otp_name
for (otp_name, _) in get_otp_images()
],
prefix = "earlgrey/fpga_cw310/standard",
tags = ["manual"],
Expand Down
16 changes: 16 additions & 0 deletions hw/ip/otp_ctrl/data/BUILD
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,10 @@ load("@rules_pkg//pkg:mappings.bzl", "pkg_files")

package(default_visibility = ["//visibility:public"])

# This package must be kept in sync with get_otp_images() from //rules:otp.bzl.
# That is, each OTP image referenced by the macro should have a definition in
# this BUILD file.

autogen_hjson_header(
name = "otp_ctrl_regs",
srcs = [
Expand Down Expand Up @@ -59,6 +63,18 @@ otp_image(
src = ":otp_ctrl_prod_json",
)

otp_json(
name = "otp_exec_disabled_json",
creator_sw_cfg_rom_exec_en = "0x0",
lc_count = 8,
lc_state = "RMA",
)

otp_image(
name = "img_exec_disabled",
src = ":otp_exec_disabled_json",
)

filegroup(
name = "all_files",
srcs = glob(["**"]),
Expand Down
8 changes: 7 additions & 1 deletion hw/ip/rom_ctrl/util/BUILD
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

load("@rules_python//python:defs.bzl", "py_binary", "py_library")
load("@rules_python//python:defs.bzl", "py_binary", "py_library", "py_test")
load("@ot_python_deps//:requirements.bzl", "requirement")

package(default_visibility = ["//visibility:public"])
Expand All @@ -22,6 +22,12 @@ py_binary(
deps = [":mem"],
)

py_test(
name = "gen_vivado_mem_image_test",
srcs = ["gen_vivado_mem_image_test.py"],
deps = [":gen_vivado_mem_image"],
)

py_binary(
name = "scramble_image",
srcs = ["scramble_image.py"],
Expand Down