Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

[top,tlgen] fabric multi-clock support #903

Merged
merged 2 commits into from Dec 4, 2019
Merged

[top,tlgen] fabric multi-clock support #903

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
9ea8623
[tlgen] Fabric multi-clock support
Nov 8, 2019
e438a60
[top] Add multiple clocks at the top.
Nov 8, 2019
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Jump to
Jump to file
Failed to load files.
Diff view
Diff view
84 changes: 56 additions & 28 deletions hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
View file
Open in desktop
Expand Up @@ -15,6 +15,10 @@
name: main
freq: "100000000"
}
{
name: fixed
freq: "100000000"
}
]
resets:
[
Expand All @@ -28,11 +32,17 @@
type: root
clk: main
}
{
name: sys_fixed
type: leaf
root: sys
clk: fixed
}
{
name: spi_device
type: leaf
root: sys
clk: main
clk: fixed
}
]
num_cores: "1"
Expand All @@ -43,11 +53,11 @@
type: uart
clock_connections:
{
clk_i: main
clk_i: fixed
}
reset_connections:
{
rst_ni: sys
rst_ni: sys_fixed
}
base_addr: 0x40000000
size: 0x1000
Expand Down Expand Up @@ -121,11 +131,11 @@
type: gpio
clock_connections:
{
clk_i: main
clk_i: fixed
}
reset_connections:
{
rst_ni: sys
rst_ni: sys_fixed
}
base_addr: 0x40010000
size: 0x1000
Expand Down Expand Up @@ -157,7 +167,7 @@
type: spi_device
clock_connections:
{
clk_i: main
clk_i: fixed
}
reset_connections:
{
Expand Down Expand Up @@ -289,11 +299,11 @@
type: rv_timer
clock_connections:
{
clk_i: main
clk_i: fixed
}
reset_connections:
{
rst_ni: sys
rst_ni: sys_fixed
}
base_addr: 0x40080000
size: 0x1000
Expand Down Expand Up @@ -577,11 +587,13 @@
clock_connections:
{
clk_main_i: main
clk_fixed_i: fixed
}
reset: sys
reset: rst_main_ni
reset_connections:
{
rst_main_ni: sys
rst_fixed_ni: sys_fixed
}
connections:
{
Expand Down Expand Up @@ -633,31 +645,35 @@
{
name: corei
type: host
clock: main
clock: clk_main_i
reset: rst_main_ni
pipeline: "false"
inst_type: rv_core_ibex
pipeline_byp: "true"
}
{
name: cored
type: host
clock: main
clock: clk_main_i
reset: rst_main_ni
pipeline: "false"
inst_type: rv_core_ibex
pipeline_byp: "true"
}
{
name: dm_sba
type: host
clock: main
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: rv_dm
pipeline: "true"
}
{
name: rom
type: device
clock: main
clock: clk_main_i
reset: rst_main_ni
pipeline: "false"
inst_type: rom
base_addr: 0x00008000
Expand All @@ -667,7 +683,8 @@
{
name: debug_mem
type: device
clock: main
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: rv_dm
base_addr: 0x1A110000
Expand All @@ -677,7 +694,8 @@
{
name: ram_main
type: device
clock: main
clock: clk_main_i
reset: rst_main_ni
pipeline: "false"
inst_type: ram_1p
base_addr: 0x10000000
Expand All @@ -687,7 +705,8 @@
{
name: eflash
type: device
clock: main
clock: clk_main_i
reset: rst_main_ni
pipeline: "false"
inst_type: eflash
base_addr: 0x20000000
Expand All @@ -697,7 +716,8 @@
{
name: uart
type: device
clock: main
clock: clk_fixed_i
reset: rst_fixed_ni
pipeline_byp: "false"
inst_type: uart
base_addr: 0x40000000
Expand All @@ -707,7 +727,8 @@
{
name: gpio
type: device
clock: main
clock: clk_fixed_i
reset: rst_fixed_ni
pipeline_byp: "false"
inst_type: gpio
base_addr: 0x40010000
Expand All @@ -717,7 +738,8 @@
{
name: spi_device
type: device
clock: main
clock: clk_fixed_i
reset: rst_fixed_ni
pipeline_byp: "false"
inst_type: spi_device
base_addr: 0x40020000
Expand All @@ -727,7 +749,8 @@
{
name: flash_ctrl
type: device
clock: main
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: flash_ctrl
base_addr: 0x40030000
Expand All @@ -737,7 +760,8 @@
{
name: rv_timer
type: device
clock: main
clock: clk_fixed_i
reset: rst_fixed_ni
pipeline_byp: "false"
inst_type: rv_timer
base_addr: 0x40080000
Expand All @@ -747,7 +771,8 @@
{
name: hmac
type: device
clock: main
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: hmac
base_addr: 0x40120000
Expand All @@ -757,7 +782,8 @@
{
name: aes
type: device
clock: main
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: aes
base_addr: 0x40110000
Expand All @@ -767,7 +793,8 @@
{
name: rv_plic
type: device
clock: main
clock: clk_main_i
reset: rst_main_ni
inst_type: rv_plic
base_addr: 0x40090000
size_byte: 0x1000
Expand All @@ -777,7 +804,8 @@
{
name: pinmux
type: device
clock: main
clock: clk_main_i
reset: rst_fixed_ni
inst_type: pinmux
base_addr: 0x40070000
size_byte: 0x1000
Expand All @@ -787,7 +815,7 @@
{
name: alert_handler
type: device
clock: main
clock: clk_main_i
inst_type: alert_handler
pipeline_byp: "false"
base_addr: 0x40130000
Expand All @@ -797,15 +825,15 @@
{
name: nmi_gen
type: device
clock: main
clock: clk_main_i
inst_type: nmi_gen
pipeline_byp: "false"
base_addr: 0x40140000
size_byte: 0x1000
pipeline: "true"
}
]
clock: main
clock: clk_main_i
}
]
interrupt_module:
Expand Down
22 changes: 12 additions & 10 deletions hw/top_earlgrey/data/top_earlgrey.hjson
View file
Open in desktop
Expand Up @@ -10,6 +10,7 @@

clocks: [
{ name: "main", freq: "100000000" }
{ name: "fixed", freq: "100000000" }
]

// Reset attributes
Expand All @@ -20,7 +21,8 @@
resets: [
{ name: "lc", type: "root", clk: "main"}
{ name: "sys", type: "root", clk: "main"}
{ name: "spi_device", type: "leaf", root: "sys", clk: "main"}
{ name: "sys_fixed", type: "leaf", root: "sys", clk: "fixed"}
{ name: "spi_device", type: "leaf", root: "sys", clk: "fixed"}
]

// Number of cores: used in rv_plic and timer
Expand All @@ -37,25 +39,25 @@
// clock connections defines the port to top level clock connection
// the ip.hjson will declare the clock port names
// If none are defined at ip.hjson, clk_i is used by default
clock_connections: {clk_i: "main"},
clock_connections: {clk_i: "fixed"},

// reset connections defines the port to top level reset connection
// the ip.hjson will declare the reset port names
// If none are defined at ip.hjson, rst_ni is used by default
reset_connections: {rst_ni: "sys"},
reset_connections: {rst_ni: "sys_fixed"},

base_addr: "0x40000000",
},
{ name: "gpio",
type: "gpio",
clock_connections: {clk_i: "main"},
reset_connections: {rst_ni: "sys"},
clock_connections: {clk_i: "fixed"},
reset_connections: {rst_ni: "sys_fixed"},
base_addr: "0x40010000",
}

{ name: "spi_device",
type: "spi_device",
clock_connections: {clk_i: "main"},
clock_connections: {clk_i: "fixed"},
reset_connections: {rst_ni: "spi_device"},
base_addr: "0x40020000",
},
Expand All @@ -67,8 +69,8 @@
},
{ name: "rv_timer",
type: "rv_timer",
clock_connections: {clk_i: "main"},
reset_connections: {rst_ni: "sys"},
clock_connections: {clk_i: "fixed"},
reset_connections: {rst_ni: "sys_fixed"},
base_addr: "0x40080000",
},
{ name: "aes",
Expand Down Expand Up @@ -151,9 +153,9 @@
// Assume xbar.hjson is located in the same directory of top.hjson
xbar: [
{ name: "main",
clock_connections: {clk_main_i: "main"},
clock_connections: {clk_main_i: "main", clk_fixed_i: "fixed"},
reset: "sys",
reset_connections: {rst_main_ni: "sys"}
reset_connections: {rst_main_ni: "sys", rst_fixed_ni: "sys_fixed"}
},
],

Expand Down