applied requested changes

VerilogCodingStyle.md

@@ -2539,24 +2539,24 @@ function automatic logic [2:0] foo(logic [2:0] a, logic [2:0] b);
 endfunction
 ```
 
-Functions should not reference any non-local signals, variables, or memories
-outside their scope. Avoiding non-local references improves readability and
-helps reduce simulation/synthesis mismatches. Accessing non-local parameters
+Functions should not reference any non-local signals or variables outside their
+scope. Avoiding non-local references improves readability and helps reduce
+simulation/synthesis mismatches. Accessing non-local parameters and constants
 is allowed.
 
 👎
 ```systemverilog {.bad}
-// - Incorrect because `MEM` is not local to get_mem()
+// - Incorrect because `mem` is not local to get_mem()
 // - Incorrect because `in_i` is not local to get_mem()
 module mymod (
   input   logic [7:0] in_i,
   output  logic [7:0] out_o
 );
 
-logic [7:0] MEM[256];
+logic [7:0] mem[256];
 
 function automatic logic [7:0] get_mem();
-  return MEM[in_i];
+  return mem[in_i];
 endfunction
 
 assign out_o = get_mem();